ST STM32F40 Series Reference Manual page 81

Embedded Flash memory interface
Bit 31 LOCK: Lock
Bits 31:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
Bit 24 EOPIE: End of operation interrupt enable
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bit 15 MER1: Mass Erase of sectors 12 to 23
Bits 14:10 Reserved, must be kept cleared.
Bits 9:8 PSIZE: Program size
Bits 7:3 SNB: Sector number
81/1422
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Erase activated of user sectors 12 to 23.
These bits select the program parallelism.
00 program x8
01 program x16
10 program x32
11 program x64
These bits select the sector to erase.
0000: sector 0
0001: sector 1
...
01011: sector 11
01100: not allowed
01101: not allowed
01110: not allowed
01111: not allowed
10000: section 12
10001: section 13
...
11011 sector 23
11100: not allowed
11101: not allowed
11110: not allowed
11111: not allowed
Doc ID 018909 Rev 4
RM0090