ST STM32F40 Series Reference Manual page 1005

Ethernet (ETH): media access control (MAC) with DMA controller
Bit 7 EDFE: Enhanced descriptor format enable
Bits 6:2 DSL: Descriptor skip length
Bit 1 DA: DMA Arbitration
Bit 0 SR: Software reset
Ethernet DMA transmit poll demand register (ETH_DMATPDR)
Address offset: 0x1004
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the transmit descriptor list.
The transmit poll demand register enables the Transmit DMA to check whether or not the
current descriptor is owned by DMA. The Transmit Poll Demand command is given to wake
up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an
underflow error in a transmitted frame or due to the unavailability of descriptors owned by
transmit DMA. You can issue this command anytime and the TxDMA resets it once it starts
re-fetching the current descriptor from host memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:0 TPD: Transmit poll demand
When these bits are written with any value, the DMA reads the current descriptor pointed to
by the ETH_DMACHTDR register. If that descriptor is not available (owned by Host),
transmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the
descriptor is available, transmission resumes.
EHERNET DMA receive poll demand register (ETH_DMARPDR)
Address offset: 0x1008
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the receive descriptor list.
The Receive poll demand register enables the receive DMA to check for new descriptors.
This command is given to wake up the RxDMA from Suspend state. The RxDMA can go into
Suspend state only due to the unavailability of descriptors owned by it.
1005/1422
When this bit is set, the enhanced descriptor format is enabled and the descriptor size is
increased to 32 bytes (8 DWORDS). This is required when time stamping is activated
(TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is activated (IPCO=1,
ETH_MACCR bit 10).
This bit specifies the number of words to skip between two unchained descriptors. The
address skipping starts from the end of current descriptor to the start of next descriptor.
When DSL value equals zero, the descriptor table is taken as contiguous by the DMA, in
Ring mode.
0: Round-robin with Rx:Tx priority given in bits [15:14]
1: Rx has priority over Tx
When this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers
and logic. It is cleared automatically after the reset operation has completed in all of the core
clock domains. Read a 0 value in this bit before re-programming any register of the core.
Doc ID 018909 Rev 4
TPD
rw_wt
9 8 7 6 5 4 3
RM0090
2 1 0