Spi_I 2 S Configuration Register (Spi_I2Scfgr) - ST STM32F40 Series Reference Manual

Serial peripheral interface (SPI)
2
27.5.8 SPI_I S configuration register (SPI_I2SCFGR)
Address offset: 0x1C
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI or I
Bit 10 I2SE: I2S Enable
2
0: I S peripheral is disabled
2
1: I S peripheral is enabled
Note: Not used in SPI mode
Bit 9:8 I2SCFG: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: This bit should be configured when the I
Not used in SPI mode
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)
Not used in SPI mode
Bit 6 Reserved: forced at 0 by hardware
Bit 5:4 I2SSTD: I2S standard selection
2
00: I S Philips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
Note: For correct operation, these bits should be configured when the I
Bit 3 CKPOL: Steady state clock polarity
2
0: I S clock steady state is low level
2
1: I S clock steady state is high level
Note: For correct operation, this bit should be configured when the I
Not used in SPI mode
843/1422
11 10 9
I2SMOD I2SE I2SCFG
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2
S standards, refer to
Doc ID 018909 Rev 4
8 7 6 5
PCMSY
NC
Reserved
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2
S is disabled
2
S is disabled.
Section 27.4.3 on page
4 3 2
I2SSTD CKPOL DATLEN
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822. Not used in SPI mode.
2
S is disabled.
2
S is disabled.
RM0090
1 0
CHLEN
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