Mac Interrupts; Figure 338. Reception With No Error; Figure 339. Reception With Errors; Figure 340. Reception With False Carrier Indication - ST STM32F40 Series Reference Manual

RM0090

Figure 338. Reception with no error

MII_RX_CLK
MII_RX_DV
MII_RXD[3:0]
MII_RX_ERR

Figure 339. Reception with errors

MII_RX_CLK
MII_RX_DV
MII_RXD[3:0]
MII_RX_ERR

Figure 340. Reception with false carrier indication

MII_RX_CLK
MII_RX_DV
MII_RXD[3:0]
MII_RX_ERR
29.5.4

MAC interrupts

Interrupts can be generated from the MAC core as a result of various events.
The ETH_MACSR register describes the events that can cause an interrupt from the MAC
core. You can prevent each event from asserting the interrupt by setting the corresponding
mask bits in the Interrupt Mask register.
Ethernet (ETH): media access control (MAC) with DMA controller
PREAMBLE SFD
PREAMBLE SFD
XX XX XX XX
Doc ID 018909 Rev 4
FCS
DA DA XX XX
0E XX XX XX
ai15634
XX
ai15635
XX
ai15636
930/1422