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ST STM32F412 Reference Manual

ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

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RM0402

Reference manual

®

STM32F412 advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the memory and the peripherals of the STM32F412 microcontrollers.

The STM32F412 is a line of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics refer to the

datasheet.



®

®

For information on the Arm

Cortex

-M4 with FPU core, refer to the Cortex

-M4 with FPU

Technical Reference Manual.

Related documents

Available from STMicroelectronics web site www.st.com:

• STM32F412xE/xG datasheet

®

• PM0214 "STM32F3 and STM32F4 Series Cortex

-M4 with FPU-M4 programming



®

manual" for information on the Arm

Cortex

-M4 with FPU.

October 2020

RM0402 Rev 6

1/1163

www.st.com

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Summary of Contents for ST STM32F412

Page 1 This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F412 microcontrollers. The STM32F412 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics refer to the datasheet.
Page 2: Table Of Contents
Contents RM0402 Contents Documentation conventions ....... . . 45 General information ......... 45 List of abbreviations for registers .
Page 3 RM0402 Contents 3.5.3 Erase ........... 64 3.5.4 Programming .
Page 4: Syscfg External Interrupt Configuration Register
Contents RM0402 5.2.2 Brownout reset (BOR) ........90 5.2.3 Programmable voltage detector (PVD) .
Page 5 RM0402 Contents 6.3.4 RCC clock interrupt register (RCC_CIR) ..... . . 128 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..130 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .
Page 6 Contents RM0402 7.3.5 I/O data bitwise handling ........173 7.3.6 GPIO locking mechanism .
Page 7 RM0402 Contents 8.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) ........190 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .
Page 8 Contents RM0402 9.5.4 DMA high interrupt flag clear register (DMA_HIFCR) ... . . 219 9.5.5 DMA stream x configuration register (DMA_SxCR) ....220 9.5.6 DMA stream x number of data register (DMA_SxNDTR) .
Page 9 RM0402 Contents 11.5 External device address mapping ......249 11.5.1 NOR/PSRAM address mapping ......249 11.6 NOR Flash/PSRAM controller .
Page 10 Contents RM0402 12.5.5 QUADSPI data length register (QUADSPI_DLR) ....309 12.5.6 QUADSPI communication configuration register (QUADSPI_CCR) . . 310 12.5.7 QUADSPI address register (QUADSPI_AR) ....312 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) .
Page 11 RM0402 Contents 13.12 ADC registers ..........333 13.12.1 ADC status register (ADC_SR) .
Page 12 Contents RM0402 14.4.13 Data unit block ......... . . 371 14.4.14 Signed data format .
Page 13 RM0402 Contents 14.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 395 14.8.16 DFSDM register map ........396 True random number generator (RNG) .
Page 14 Contents RM0402 16.3.6 Input capture mode ........434 16.3.7 PWM input mode .
Page 15 RM0402 Contents 16.4.21 TIM1&TIM8 register map ........482 General-purpose timers (TIM2 to TIM5) .
Page 16 Contents RM0402 17.4.15 TIMx capture/compare register 3 (TIMx_CCR3) ....539 17.4.16 TIMx capture/compare register 4 (TIMx_CCR4) ....539 17.4.17 TIMx DMA control register (TIMx_DCR) .
Page 17 RM0402 Contents 18.4.10 TIM9/12 auto-reload register (TIMx_ARR) ..... 577 18.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) ....578 18.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) .
Page 18 Contents RM0402 19.4.9 TIM6/7 register map ........604 Independent watchdog (IWDG) .
Page 19 RM0402 Contents 22.3.5 RTC initialization and configuration ......622 22.3.6 Reading the calendar ........624 22.3.7 Resetting the RTC .
Page 20 Contents RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface ..656 23.1 Introduction ..........656 23.2 FMPI2C main features .
Page 21 RM0402 Contents 23.7.12 FMPI2C register map ........721 Inter-integrated circuit (I C) interface .
Page 22 Contents RM0402 25.4.1 USART character description ....... 763 25.4.2 Transmitter ..........764 25.4.3 Receiver .
Page 23 RM0402 Contents 26.3.6 Communication formats ........821 26.3.7 SPI configuration .
Page 24 Contents RM0402 27.1 SDIO main features ........863 27.2 SDIO bus topology .
Page 25 RM0402 Contents 27.8 SDIO registers ..........905 27.8.1 SDIO power control register (SDIO_POWER) .
Page 26 Contents RM0402 28.7.1 Transmission handling ........928 28.7.2 Time triggered communication mode .
Page 27 RM0402 Contents 29.6.3 Peripheral endpoints ........976 29.7 OTG_FS as a USB host .
Page 28 Contents RM0402 29.15.15 OTG general core configuration register (OTG_GCCFG) ..1019 29.15.16 OTG core ID register (OTG_CID) ......1021 29.15.17 OTG core LPM configuration register (OTG_GLPMCFG) .
Page 29 RM0402 Contents 29.15.44 OTG device IN endpoint x control register (OTG_DIEPCTLx) ..1048 29.15.45 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) ..1051 29.15.46 OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) .
Page 30 Contents RM0402 30.6 ID codes and locking mechanism ......1130 30.6.1 MCU device ID code ........1130 30.6.2 Boundary scan TAP .
Page 31 RM0402 Contents 30.17.3 TPUI formatter ......... . 1149 30.17.4 TPUI frame synchronization packets .
Page 32 List of tables RM0402 List of tables Table 1. Register boundary addresses ..........51 Table 2.
Page 33 RM0402 List of tables Table 49. NOR Flash/PSRAM: example of supported memories and transactions ............254 Table 50.
Page 34 List of tables RM0402 with break feature ............474 Table 98.
Page 35 RM0402 List of tables oversampling by 16............776 Table 143.
Page 36 List of tables RM0402 Table 187. R4 response ............901 Table 188.
Page 37 RM0402 List of figures List of figures Figure 1. System architecture ............47 Figure 2.
Page 38 List of figures RM0402 Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) ... 275 Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)....277 Figure 51.
Page 39 RM0402 List of figures Figure 99. TI2 external clock connection example........429 Figure 100.
Page 40 List of figures RM0402 Figure 151. Capture/compare channel 1 main circuit ........500 Figure 152.
Page 41 RM0402 List of figures Figure 201. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)............. 597 Figure 202.
Page 42 List of figures RM0402 Figure 249. Start bit detection when oversampling by 16 or 8 ....... 767 Figure 250.
Page 43 RM0402 List of figures Figure 298. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 ....842 Figure 299. Example of 16-bit data frame extended to 32-bit channel frame ....842 Figure 300.
Page 44 List of figures RM0402 Figure 350. Isochronous IN transactions ..........1093 Figure 351.
Page 45: Documentation Conventions
RM0402 Documentation conventions Documentation conventions General information ®(a) ® The STM32F412xx devices have an Arm Cortex -M4 with FPU core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit.
Page 46: Glossary
Documentation conventions RM0402 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.
Page 47: System And Memory Overview
RM0402 System and memory overview System and memory overview System architecture In STM32F412xx, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Six masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus – DMA1 memory bus –...
Page 48: I-Bus
System and memory overview RM0402 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM1).
Page 49: Memory Organization
RM0402 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 50: Memory Map And Register Boundary Addresses
RM0402 2.2.2 Memory map and register boundary addresses Figure 2. Memory map Reserved 0xE010 0000 - 0xFFFF FFFF Cortex -M4 internal 0xE000 0000 - 0xE00F FFFF peripherals 0xA000 2000 – 0DFFF FFF Reserved 0xA000 1FFF AHB3 0x6000 0000 0x5FFF FFFF AHB2 0x5000 0000 Reserved...
Page 51: Table 1. Register Boundary Addresses
RM0402 The following table gives the boundary addresses of the peripherals available in the devices. Table 1. Register boundary addresses Boundary address Peripheral 0xE010 0000 - 0xFFFF FFFF Reserved ® Cortex 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 2000 - 0xDFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF QuadSPI control register...
Page 52 RM0402 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4001 6400- 0x4001 FFFF Reserved 0x4001 6000 - 0x4001 63FF DFSDM1 0x4001 5400 - 0x4001 5FFF Reserved 0x4001 5000 - 0x4001 53FF SPI5/I2S5 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9...
Page 53: Embedded Sram
RM0402 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF I2CFMP1 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2...
Page 54: Flash Memory Overview
RM0402 (Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller). To get the max performance on SRAM execution, physical remap should be selected (boot or software selection). Flash memory overview The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory.
Page 55: Boot Configuration
RM0402 Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM1 address 0x20000300 (0x01: bit set; 0x00: bit reset). ® For more information on bit-banding, refer to the Cortex -M4 with FPU programming manual (see Related documents on page Boot configuration...
Page 56: Table 3. Embedded Bootloader Interfaces
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz). The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606.
Page 57 RM0402 Table 4. Memory mapping vs. Boot mode/physical remap in STM32F412xx Boot/Remap in main Boot/Remap in Boot/Remap in Addresses Flash memory embedded SRAM System memory 0x0400 000 - 0x07FF FFFF Reserved Reserved Reserved SRAM1 (256 KB) System memory 0x0000 0000 - 0x0003 FFFF Flash (1M) Aliased Aliased (30 KB) Aliased...
Page 58: Embedded Flash Memory Interface
Embedded Flash memory interface RM0402 Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 59: Embedded Flash Memory
RM0402 Embedded Flash memory interface Embedded Flash memory The Flash memory has the following main features: • Capacity up to 1 Mbyte • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •...
Page 60: Read Interface
Embedded Flash memory interface RM0402 Read interface 3.4.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device.
Page 61: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
RM0402 Embedded Flash memory interface Decreasing the CPU frequency Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register Program the new number of wait states to the LATENCY bits in FLASH_ACR...
Page 62: Figure 4. Sequential 32-Bit Instruction Execution
Embedded Flash memory interface RM0402 Figure 4. Sequential 32-bit instruction execution WAIT Without prefetch WAIT ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8 fetch fetch fetch fetch fetch fetch fetch fetch Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8 Wait data With prefetch...
Page 63: Erase And Program Operations
RM0402 Embedded Flash memory interface Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. This feature can be enabled by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register.
Page 64: Program/Erase Parallelism
Embedded Flash memory interface RM0402 3.5.2 Program/erase parallelism The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external V supply is used or not.
Page 65: Programming
RM0402 Embedded Flash memory interface Mass Erase To perform Mass Erase, the following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set the MER bit in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be cleared Note:...
Page 66: Interrupts
Embedded Flash memory interface RM0402 Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution.
Page 67: Table 10. Description Of The Option Bytes
RM0402 Embedded Flash memory interface Table 10. Description of the option bytes Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0xAA: Level 0, no protection Bits 15:8 0xCC: Level 2, chip protection (debug and boot from RAM features disabled) Others: Level 1, read protection of memories (debug features limited)
Page 68: Programming User Option Bytes
Embedded Flash memory interface RM0402 Table 10. Description of the option bytes nWRP: Flash memory write protection option bytes sector 0 to 11 can be write protected nWRPi If SPRMOD is reset (default value): 0: Write protection active on sector i. Bits 11:0 1: Write protection not active on sector i.
Page 69 RM0402 Embedded Flash memory interface Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM). • Level 1: read protection enabled It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte.
Page 70: Write Protections
Embedded Flash memory interface RM0402 Table 11. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory Level 2 Level 1 Option Bytes...
Page 71: Proprietary Code Readout Protection (Pcrop)
RM0402 Embedded Flash memory interface If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register.
Page 72: Figure 6. Pcrop Levels
Embedded Flash memory interface RM0402 Figure 6. PCROP levels Write options SPMOD = active and valid nWRPi* Level 1 RDP /= 0xAA RDP /= 0xCC Write options default Write options No restriction on SPMOD = active SPMOD = active Write options and valid nWRPi* and valid nWRPi* Level 2...
Page 73: One-Time Programmable Bytes
RM0402 Embedded Flash memory interface One-time programmable bytes Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area. Table 12. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP0 OTP0 OTP0 OTP0 0x1FFF 7800 OTP0 OTP0...
Page 74: Flash Interface Registers
Embedded Flash memory interface RM0402 Flash interface registers 3.8.1 Flash access control register (FLASH_ACR) The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res.
Page 75: Flash Key Register (Flash_Keyr)
RM0402 Embedded Flash memory interface 3.8.2 Flash key register (FLASH_KEYR) The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations. Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access KEY[31:16] KEY[15:0] Bits 31:0 FKEYR: FPEC key...
Page 76: Flash Status Register (Flash_Sr)
Embedded Flash memory interface RM0402 3.8.4 Flash status register (FLASH_SR) The Flash status register gives information on ongoing program and erase operations. Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res.
Page 77: Flash Control Register (Flash_Cr)
RM0402 Embedded Flash memory interface Bits 3:2 Reserved, must be kept cleared. Bit 1 OPERR: Operation error Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1).
Page 78: Flash Option Control Register (Flash_Optcr)
Embedded Flash memory interface RM0402 Bits 9:8 PSIZE: Program size These bits select the program parallelism. 00 program x8 01 program x16 10 program x32 11 program x64 Bit 7 Reserved, must be kept cleared. Bits 6:3 SNB: Sector number These bits select the sector to erase.
Page 79 RM0402 Embedded Flash memory interface Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits 0: PCROP disabled, nWPRi bits used for Write Protection on sector i 1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i Bits 30:28 Reserved, must be kept cleared. Bits 27:16 nWRP[11:0]: Not write protect These bits contain the value of the write-protection option bytes of sectors after reset.
Page 80 Embedded Flash memory interface RM0402 Bits 3:2 BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V drops below the selected BOR level, a device reset is generated.
Page 81: Flash Interface Register Map
RM0402 Embedded Flash memory interface 3.8.7 Flash interface register map Table 13. Flash register map and reset values Offset Register FLASH_ACR LATENCY 0x00 Reset value FLASH_KEYR KEY[31:16] KEY[15:0] 0x04 Reset value 0 0 0 FLASH_ OPTKEYR[31:16] OPTKEYR[15:0] OPTKEYR 0x08 Reset value 0 0 0 FLASH_SR 0x0C...
Page 82: Crc Calculation Unit
CRC calculation unit RM0402 CRC calculation unit CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 83: Crc Registers
RM0402 CRC calculation unit Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses.
Page 84: Independent Data Register (Crc_Idr)
CRC calculation unit RM0402 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] Bits 31:8 Reserved, must be kept at reset value.
Page 85: Crc Register Map
RM0402 CRC calculation unit 4.4.4 CRC register map Table 14. CRC calculation unit register map and reset values Offset Register CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register 0x04 Reset value 0x0000 CRC_CR 0x08 Reset value Refer to Section 2.2 on page 49 for the register boundary addresses.
Page 86: Power Controller (Pwr)
Power controller (PWR) RM0402 Power controller (PWR) Power supplies There are two main power supply schemes: • VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins.
Page 87: Independent A/D Converter Supply And Reference Voltage
RM0402 Power controller (PWR) Figure 8. Power supply overview Backup circuitry Power (OSC32K,RTC, 1.65 to 3.6V switch Wakeup logic Backup registers) GPIOs Logic Kernel logic CAP_1 (CPU, digital 2 × 2.2 μF CAP_2 & RAM) 1/2/...11/12 Voltage regulator 11 × 100 nF + 1 ×...
Page 88 Power controller (PWR) RM0402 To allow the RTC to operate even when the main digital supply (V ) is turned off, the V pin powers the following blocks: • The RTC • The LSE oscillator • PC13 to PC15 I/Os The switch to the V supply is controlled by the power-down reset embedded in the Reset block.
Page 89: Voltage Regulator
RM0402 Power controller (PWR) Backup domain access After reset, the backup domain (RTC registers, and RTC backup register) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows: • Access to the RTC and RTC backup registers Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 6.3.12: RCC AHB3 peripheral clock enable register...
Page 90: Power Supply Supervisor
Power controller (PWR) RM0402 Note: For more details, refer to the voltage regulator section in the STM32F412xx datasheet. Power supply supervisor 5.2.1 Power-on reset (POR)/power-down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V. To use the device below 1.8 V, the internal power supervisor must be switched off using the PDR_ON pin (please refer to section Power supply supervisor of the STM32F412xx datasheet).
Page 91: Programmable Voltage Detector (Pvd)
RM0402 Power controller (PWR) When the supply voltage (V ) drops below the selected V threshold, a device reset is generated. The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR or by an external power supervisor if the PDR is switched off through the PDR_ON pin (see Section 5.2.1: Power-on reset (POR)/power-down reset...
Page 92: Low-Power Modes
Power controller (PWR) RM0402 Figure 11. PVD thresholds 100 mV PVD threshold hysteresis PVD output MS30432V2 Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 93 RM0402 Power controller (PWR) Exiting low-power mode The MCU exits from Sleep and Stop modes low-power mode depending on the way the low- power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
Page 94: Slowing Down System Clocks
Power controller (PWR) RM0402 Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. Table 15. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup Voltage regulator domain clocks domain clocks WFI or Return Sleep and Any interrupt CPU CLK OFF...
Page 95: Sleep Mode
RM0402 Power controller (PWR) 5.3.3 Sleep mode Entering Sleep mode The Sleep mode is entered according to Entering low-power mode, when the SLEEPDEEP ® bit in the Cortex -M4 with FPU System Control register is cleared. Refer to Table 16 Table 17 for details on how to enter Sleep mode.
Page 96: Batch Acquisition Mode
Power controller (PWR) RM0402 Table 17. Sleep-on-exit entry and exit (continued) Sleep-on-exit Description Mode exit Interrupt: refer to Table 40: Vector table for STM32F412xx Wakeup latency None 5.3.4 Batch acquisition mode Entering BAM The BAM is entered according to Section : Entering low-power mode, when the ®...
Page 97: Stop Mode
RM0402 Power controller (PWR) Table 19. BAM-on-exit entry and exit Sleep-on-exit Description Set the Flash memory in low-power mode: – FISSR/FMSSR and FPDS bits of the PWR_CR register WFI (wait for interrupt) while: Mode entry – SLEEPDEEP = 0 and –...
Page 98: Table 20. Stop Operating Modes
Power controller (PWR) RM0402 Table 20. Stop operating modes Stop mode MRLV bit LPLV bit FPDS bit LPDS bit Wakeup latency STOP MR HSI RC startup time HSI RC startup time + STOP MRFPD Flash wakeup time from Deep Power Down mode HSI RC startup time + STOP LP regulator wakeup time from LP...
Page 99: Table 21. Stop Mode Entry And Exit
RM0402 Power controller (PWR) In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 21.3 Section 21: Window watchdog (WWDG).
Page 100: Standby Mode
Power controller (PWR) RM0402 Table 21. Stop mode entry and exit Stop mode Description If WFI or Return from ISR was used for entry: Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability.
Page 101: Programming The Rtc Alternate Functions To Wake Up The Device From The Stop And Standby Modes
RM0402 Power controller (PWR) Refer to Table 22 for more details on how to exit Standby mode. Table 22. Standby mode entry and exit Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP is set in Cortex -M4 with FPU System Control register, –...
Page 102 Power controller (PWR) RM0402 These RTC alternate functions can wake up the system from the Stop and Standby low- power modes. The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.
Page 103 RM0402 Power controller (PWR) Configure the RTC to detect the tamper or time stamp event • To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: Enable the RTC wakeup interrupt in the RTC_CR register Configure the RTC to generate the RTC wakeup event Safe RTC alternate function wakeup flag clearing sequence If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared,...
Page 104: Power Control Registers
Power controller (PWR) RM0402 Power control registers 5.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FISSR FMSSR Res. Res. Res.
Page 105 RM0402 Power controller (PWR) Bit 12 Reserved, must be kept at reset value. Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep 0: Main regulator in Voltage scale 3 when the device is in Stop mode. 1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode.
Page 106: Pwr Power Control/Status Register (Pwr_Csr)
Power controller (PWR) RM0402 Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters deepsleep.
Page 107 RM0402 Power controller (PWR) Bit 7 EWUP2: Enable WKUP2 pin (PC0) This bit is set and cleared by software. 0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode. 1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).
Page 108: Pwr Register Map
Power controller (PWR) RM0402 PWR register map The following table summarizes the PWR registers. Table 23. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2 on page 49 for the register boundary addresses.
Page 109: Reset And Clock Control (Rcc) For Stm32F412Xx
RM0402 Reset and clock control (RCC) for STM32F412xx Reset and clock control (RCC) for STM32F412xx Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 6.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain.
Page 110: Power Reset
In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode. For further information on the user option bytes, refer to the STM32F412xx Flash programming manual available from your ST sales office. 6.1.2 Power reset...
Page 111: Backup Domain Reset
RM0402 Reset and clock control (RCC) for STM32F412xx 6.1.3 Backup domain reset The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register...
Page 112: Figure 13. Clock Tree
Reset and clock control (RCC) for STM32F412xx RM0402 Figure 13. Clock tree Enable Not (sleep or deep sleep) IWDGCLK watchdog LSI RC CPU clock 32 kHz Not deepsleep RTC / AWU FCLK Cortex RTC / AWU enable free-running clock OSC32_IN clock LSE OSC Peripheral...
Page 113: Hse Clock
RM0402 Reset and clock control (RCC) for STM32F412xx The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB OTG FS, I2S and SDIO.
Page 114: Hsi Clock
Reset and clock control (RCC) for STM32F412xx RM0402 Figure 14. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HI-Z) External source OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. You select this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR).
Page 115: Pll Configuration
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 116: Lsi Clock
Reset and clock control (RCC) for STM32F412xx RM0402 The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain control register (RCC_BDCR). The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not.
Page 117: Rtc/Awu Clock
RM0402 Reset and clock control (RCC) for STM32F412xx CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
Page 118: Clock-Out Capability
Reset and clock control (RCC) for STM32F412xx RM0402 6.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): –...
Page 119: Figure 15. Frequency Measurement With Tim5 In Input Capture Mode
RM0402 Reset and clock control (RCC) for STM32F412xx The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. It is also possible to measure the LSI frequency: this is useful for applications that do not have a crystal.
Page 120: Figure 16. Frequency Measurement With Tim11 In Input Capture Mode
Reset and clock control (RCC) for STM32F412xx RM0402 Internal/external clock measurement using TIM11 channel1 TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register.
Page 121: Rcc Registers
RM0402 Reset and clock control (RCC) for STM32F412xx RCC registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 6.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX81 where X is undefined. Access: no wait state, word, half-word and byte access PLLI2S PLLI2S...
Page 122 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
Page 123: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •...
Page 124 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled. 0: HSI clock selected as PLL and PLLI2S clock entry 1: HSE oscillator clock selected as PLL and PLLI2S clock entry Bits 21:18 Reserved, must be kept at reset value.
Page 125: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0402 Reset and clock control (RCC) for STM32F412xx Bits 5:0 PLLM[5:0]: Division factor for the main PLL (PLL) input clock Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO. These bits can be written only when the PLL and PLLI2S are disabled. Caution: The software has to set these bits correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz.
Page 126 Reset and clock control (RCC) for STM32F412xx RM0402 Bits 29:27 MCO2PRE[1:0]: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs.
Page 127 RM0402 Reset and clock control (RCC) for STM32F412xx Bits 12:10 PPRE1[2:0]: APB Low speed prescaler (APB1) Set and cleared by software to control APB low-speed clock division factor. Caution: The software has to set these bits correctly not to exceed 50 MHz on this domain. The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after PPRE1 write.
Page 128: Rcc Clock Interrupt Register (Rcc_Cir)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.4 RCC clock interrupt register (RCC_CIR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access PLLI2S Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res.
Page 129 RM0402 Reset and clock control (RCC) for STM32F412xx Bits 15:14 Reserved, must be kept at reset value. Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLLI2S lock. 0: PLLI2S lock interrupt disabled 1: PLLI2S lock interrupt enabled Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock.
Page 130: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) for STM32F412xx RM0402 Bit 3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is...
Page 131 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 12 CRCRST: CRC reset Set and cleared by software. 0: does not reset CRC 1: resets CRC Bits 11:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset Set and cleared by software.
Page 132: Rcc Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 133: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 134 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: does not reset CAN2 1: resets CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: does not reset CAN1 1: resets CAN1 Bit 24 I2CFMP1RST: I2CFMP1 reset Set and cleared by software.
Page 135 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: does not reset the window watchdog 1: resets the window watchdog Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14RST: TIM14 reset Set and cleared by software.
Page 136: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. DFSDM1 SPI5 TIM11 TIM10 TIM9 Res. Res. Res. Res. Res.
Page 137 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: does not reset SPI1 1: resets SPI1 Bit 11 SDIORST: SDIO reset Set and cleared by software. 0: does not reset the SDIO module 1: resets the SDIO module Bits 10:9 Reserved, must be kept at reset value.
Page 138: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x30 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 139 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 3 GPIODEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software.
Page 140: Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) Address offset: 0x34 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 141: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 142 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 26 CAN2EN: CAN 2 clock enable This bit is set and cleared by software. 0: CAN 2 clock disabled 1: CAN 2 clock enabled Bit 25 CAN1EN: CAN 1 clock enable This bit is set and cleared by software.
Page 143 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10 RTC APB: clock enable Set and cleared by software. 0: RTC APB clock disabled 1: RTC APB clock enabled (default value).
Page 144: Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 8000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 DFSDM1 Res. Res. Res. Res. Res.
Page 145 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 13 SPI4EN: SPI4 clock enable Set and reset by software. 0: SPI4 clock disabled 1: SPI4 clock enable Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 SDIOEN: SDIO clock enable Set and cleared by software.
Page 146: Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.15 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x0061 90FF Access: no wait state, word, half-word and byte access. DMA2 DMA1 SRAM1 Res. Res.
Page 147 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode Set and cleared by software. 0: IO port G clock disabled during Sleep mode 1: IO port G clock enabled during Sleep mode Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode Set and cleared by software.
Page 148: Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.16 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) Address offset: 0x54 Reset value: 0x0000 00C0 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res.
Page 149 RM0402 Reset and clock control (RCC) for STM32F412xx Bits 31:2 Reserved, must be kept at reset value. Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode Set and cleared by software. 0: QUADSPI module clock disabled during Sleep mode 1: QUADSPI module clock enabled during Sleep mode Bit 0 FSMCLPEN: Flexible memory controller module clock enable during Sleep mode Set and cleared by software.
Page 150: Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.18 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0x17E6 CDFF Access: no wait state, word, half-word and byte access. CAN2 CAN1 I2CFMP1 I2C3 I2C2 I2C1 USART3...
Page 151 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 18 USART3LPEN: USART3 clock enable during Sleep mode Set and cleared by software. 0: USART3 clock disabled during Sleep mode 1: USART3 clock enabled during Sleep mode Bit 17 USART2LPEN: USART2 clock enable during Sleep mode Set and cleared by software.
Page 152 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode Set and cleared by software. 0: TIM6 clock disabled during Sleep mode 1: TIM6 clock enabled during Sleep mode Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode Set and cleared by software.
Page 153: Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.19 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0117 F933 Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM10 TIM9 DFSDM1 Res.
Page 154 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode Set and cleared by software. 0: System configuration controller clock disabled during Sleep mode 1: System configuration controller clock enabled during Sleep mode Bit 13 SPI4LPEN: SPI4 clock enable during sleep mode Set and reset by software.
Page 155: Rcc Backup Domain Control Register (Rcc_Bdcr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.20 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 wait state 3, word, half-word and byte access ≤ ≤ Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC Backup domain control register (RCC_BDCR)
Page 156: Rcc Clock Control & Status Register (Rcc_Csr)
Reset and clock control (RCC) for STM32F412xx RM0402 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 157 RM0402 Reset and clock control (RCC) for STM32F412xx Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
Page 158: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. The RCC_SSCGR register must be written either before the main PLL is enabled or after the main PLL disabled.
Page 159: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) Address offset: 0x84 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLI2S clock outputs according to the formulas: •...
Page 160 Reset and clock control (RCC) for STM32F412xx RM0402 Bit 22 PLLI2SSRC: PLLI2S entry clock source Set and cleared by software to select PLLI2S clock source. This bit can be written only when PLLI2S is disabled. 0: HSE or HSI depending on PLLSRC of PLLCFGR 1: external AFI clock (CK_I2S_EXT) selected as PLL clock entry Bits 21:15 Reserved, must be kept at reset value.
Page 161: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr)
RM0402 Reset and clock control (RCC) for STM32F412xx 6.3.24 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) Address offset: 0x8C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. CKDFSD Res. Res. I2S2RC[1:0] I2S1RC[1:0] TIMPRE Res. Res. Res. Res.
Page 162: Rcc Clocks Gated Enable Register (Ckgatenr)
Reset and clock control (RCC) for STM32F412xx RM0402 Bits 23: 16 Reserved, must be kept at reset value. Bit 15 CKDFSDM1ASEL: DFSDM1 audio clock selection. 0: CK_I2S_APB1 selected as audio clock 1: CK_I2S_APB2 selected as audio clock Bits 14:0 Reserved, must be kept at reset value. 6.3.25 RCC clocks gated enable register (CKGATENR) Address offset: 0x90...
Page 163: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr2)
RM0402 Reset and clock control (RCC) for STM32F412xx Bit 2 CM4DBG_CKEN: Cortex M4 ETM clock enable 0: the clock gating is enabled 1: the clock gating is disabled, the clock is always enabled. Bit 1 AHB2APB2_CKEN: AHB to APB2 Bridge clock enable 0: the clock gating is enabled 1: the clock gating is disabled, the clock is always enabled.
Page 164: Rcc Register Map
Reset and clock control (RCC) for STM32F412xx RM0402 6.3.27 RCC register map Table 24 gives the register map and reset values Table 24. RCC register map and reset values for STM32F412xx Addr. Register offset name 0x00 RCC_CR HSICAL[7:0] HSITRIM[4:0] RCC_ 0x04 PLLR[2:0] PLLQ[3:0]...
Page 165 RM0402 Reset and clock control (RCC) for STM32F412xx Table 24. RCC register map and reset values for STM32F412xx (continued) Addr. Register offset name RCC_ 0x38 AHB3ENR 0x3C Reserved RCC_ 0x40 APB1ENR RCC_ 0x44 APB2ENR 0x48 Reserved 0x4C Reserved RCC_ 0x50 AHB1LPENR RCC_ 0x54...
Page 166 Reset and clock control (RCC) for STM32F412xx RM0402 Table 24. RCC register map and reset values for STM32F412xx (continued) Addr. Register offset name 0x80 RCC_SSCGR INCSTEP[14:0] MODPER[11:0] RCC_ 0x84 PLLI2SN[8:0]] PLLI2SM[5:0] PLLI2SCFGR 0x88 Reserved RCC_ 0x8C DCKCFGR 0x90 CKGATENR RCC_ 0x94 DCKCFGR2 Refer to...
Page 167: General-Purpose I/Os (Gpio)
RM0402 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).
Page 168: Table 25. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0402 Figure 17 show the basic structure of a 5 V tolerant I/O port bit. Table 25 gives the possible port bit configurations. Figure 17. Basic structure of a five-volt tolerant I/O port bit Analog To on-chip peripheral Alternate function input on/off...
Page 169: General-Purpose I/O (Gpio)
RM0402 General-purpose I/Os (GPIO) Table 25. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog...
Page 170: I/O Pin Multiplexer And Mapping
General-purpose I/Os (GPIO) RM0402 7.3.2 I/O pin multiplexer and mapping The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin. Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:...
Page 171: Table 26. Flexible Swj-Dp Pin Assignment
RM0402 General-purpose I/Os (GPIO) Table 26. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled...
Page 172: Figure 18. Selecting An Alternate Function On Stm32F412Xx
General-purpose I/Os (GPIO) RM0402 Figure 18. Selecting an alternate function on STM32F412xx For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3/5) AF3 (TIM8/9) AF4 (I2C1..3, I2CFMP1) AF5 (SPI1/2/3/4) AF6 (SPI2/3/4, DFSDM) Pin x (x = 0..7) AF7 (SPI2, USART1..3) AF8 (DFSDM, USART3/6, CAN1)
Page 173: I/O Port Control Registers
RM0402 General-purpose I/Os (GPIO) 7.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction).
Page 174: I/O Alternate Function Input/Output
General-purpose I/Os (GPIO) RM0402 The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A...H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 175: Output Configuration
RM0402 General-purpose I/Os (GPIO) Figure 19. Input floating/pull up/pull down configurations Read V DD V DD on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull diode down V SS V SS Read/write ai15940b 7.3.10 Output configuration...
Page 176: Alternate Function Configuration
General-purpose I/Os (GPIO) RM0402 Figure 20. Output configuration Read TTL Schmitt trigger on/off protection Write diode Input driver pull I/O pin Output driver on/off P-MOS protection pull down diode Output control Read/write N-MOS Push-pull or Open-drain ai15941b 7.3.11 Alternate function configuration When the I/O port is programmed as alternate function: •...
Page 177: Analog Configuration
RM0402 General-purpose I/Os (GPIO) 7.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 178: Selection Of Rtc Additional Functions
General-purpose I/Os (GPIO) RM0402 7.3.15 Selection of RTC additional functions The STM32F4xx feature one GPIO pin RTC_AF1 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs. • The RTC_AF1 (PC13) can be used for the following purposes: RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register •...
Page 179: Gpio Registers
RM0402 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 7.4.1 GPIO port mode register (GPIOx_MODER) (x = A...H) Address offset: 0x00...
Page 180: Gpio Port Output Speed Register (Gpiox_Ospeedr)
General-purpose I/Os (GPIO) RM0402 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A...H) Address offset: 0x08 Reset values: • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10...
Page 181: Gpio Port Input Data Register (Gpiox_Idr) (X = A
RM0402 General-purpose I/Os (GPIO) 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A...H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 182: Gpio Port Configuration Lock Register (Gpiox_Lckr)
General-purpose I/Os (GPIO) RM0402 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
Page 183: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A
RM0402 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 184: (X = A
General-purpose I/Os (GPIO) RM0402 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A...H) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0...
Page 185 RM0402 General-purpose I/Os (GPIO) Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_ OTYPER 0x04 (where x = A...H) Reset value GPIOx_ OSPEEDR (where x = 0x08 C...H) Reset value GPIOA_ OSPEEDER 0x08 Reset value GPIOB_ OSPEEDR 0x08 Reset value GPIOA_PUPDR...
Page 186 General-purpose I/Os (GPIO) RM0402 Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_LCKR (where x = A...H) 0x1C Reset value GPIOx_AFRL AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] (where x = A...H) 0x20 Reset value GPIOx_AFRH AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]...
Page 187: System Configuration Controller (Syscfg)
RM0402 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t commutation to reduce the I/O noise on power...
Page 188: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0402 Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins.
Page 189: Syscfg External Interrupt Configuration Register 1
RM0402 System configuration controller (SYSCFG) 8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 190: Syscfg External Interrupt Configuration Register 3
System configuration controller (SYSCFG) RM0402 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 191: (Syscfg_Exticr4)
RM0402 System configuration controller (SYSCFG) 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 192: Compensation Cell Control Register (Syscfg_Cmpcr)
System configuration controller (SYSCFG) RM0402 Bit 2 PVDL: PVD lock This bit is set by software. It can be cleared only by a system reset. It enables and locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the PVDE and PVDS[2:0] bits of PWR_CR register.
Page 193: Syscfg Configuration Register (Syscfg_Cfgr)
RM0402 System configuration controller (SYSCFG) 8.2.9 SYSCFG configuration register (SYSCFG_CFGR) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 194: Syscfg Register Map
System configuration controller (SYSCFG) RM0402 8.2.10 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 29. SYSCFG register map and reset values Offset Register SYSCFG_ MEMRMP 0x00 Reset value SYSCFG_PMC 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0]...
Page 195: Direct Memory Access Controller (Dma)
RM0402 Direct memory access controller (DMA) Direct memory access controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action.
Page 196 Direct memory access controller (DMA) RM0402 – DMA flow controller: the number of data items to be transferred is software- programmable from 1 to 65535 – Peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware •...
Page 197: Dma Functional Description
RM0402 Direct memory access controller (DMA) DMA functional description 9.3.1 DMA block diagram The figure below shows the block diagram of a DMA. Figure 23. DMA block diagram DMA controller REQ_STR0_CH0 Memory port REQ_STR0_CH1 REQ_STR0_CH7 REQ_STR1_CH0 REQ_STR1_CH1 REQ_STREAM0 REQ_STREAM1 REQ_STR1_CH7 REQ_STREAM2 REQ_STREAM3 REQ_STREAM4...
Page 198: Dma Transactions
Direct memory access controller (DMA) RM0402 9.3.3 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software- programmable.
Page 199: Table 30. Dma1 Request Mapping
RM0402 Direct memory access controller (DMA) The 8 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently connected to each channel and their connection depends on the product implementation. Table 30 Table 31 give examples of DMA request mappings. Table 30.
Page 200: Arbiter
Direct memory access controller (DMA) RM0402 9.3.5 Arbiter An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. Priorities are managed in two stages: •...
Page 201 RM0402 Direct memory access controller (DMA) Table 32. Source and destination address (continued) Bits DIR[1:0] of the Direction Source address Destination address DMA_SxCR register Memory-to-memory DMA_SxPAR DMA_SxM0AR Reserved When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively.
Page 202: Figure 25. Peripheral-To-Memory Mode
Direct memory access controller (DMA) RM0402 Figure 25. Peripheral-to-memory mode DMA_SxM0AR DMA controller DMA_SxM1AR AHB memory Memory bus port Memory destination FIFO Arbiter level FIFO REQ_STREAMx AHB peripheral Peripheral bus port peripheral source DMA_SxPAR Peripheral DMA request ai15948 1. For double-buffer mode. Memory-to-peripheral mode Figure 26 describes this mode.
Page 203: Figure 26. Memory-To-Peripheral Mode
RM0402 Direct memory access controller (DMA) Figure 26. Memory-to-peripheral mode DMA_SxM0AR DMA controller DMA_SxM1AR Memory bus AHB memory port Memory source FIFO Arbiter level FIFO REQ_STREAMx AHB peripheral Peripheral bus port Peripheral destination DMA_SxPAR Peripheral DMA request ai15949 1. For double-buffer mode. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral.
Page 204: Pointer Incrementation
Direct memory access controller (DMA) RM0402 Figure 27. Memory-to-memory mode DMA_SxM0AR DMA controller DMA_SxM1AR AHB memory Memory bus port Memory 2 destination Arbiter FIFO FIFO level Stream enable FIFO AHB peripheral Peripheral bus port Memory 1 source DMA_SxPAR ai15950 1. For double-buffer mode. 9.3.8 Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented or kept...
Page 205: Circular Mode
RM0402 Direct memory access controller (DMA) 9.3.9 Circular mode The circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served.
Page 206: Programmable Data Width, Packing/Unpacking, Endianness
Direct memory access controller (DMA) RM0402 memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the double-buffer mode), the memory address registers are write-protected as soon as the stream is enabled.
Page 207: Single And Burst Transfers
RM0402 Direct memory access controller (DMA) Table 34. Packing/unpacking and endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane of data Memory Memory port Peripheral memory peripheral items to transfer address / byte transfer port port PINCOS = 1...
Page 208: Fifo
Direct memory access controller (DMA) RM0402 The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register. The burst size indicates the number of beats in the burst, not the number of bytes transferred.
Page 209: Figure 28. Fifo Structure
RM0402 Direct memory access controller (DMA) The structure of the FIFO differs depending on the source and destination data widths, and is described in the figure below. Figure 28. FIFO structure 4 words Empty Full byte lane 3 B 11 Source: byte Destination: word byte lane 2...
Page 210: Table 36. Fifo Threshold Configurations
Direct memory access controller (DMA) RM0402 FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers.
Page 211: Dma Transfer Completion
RM0402 Direct memory access controller (DMA) FIFO flush The FIFO can be flushed when the stream is disabled by resetting the EN bit in the DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers. If some data are still present in the FIFO when the stream is disabled, the DMA controller continues transferring the remaining data to the destination (even though stream is effectively disabled).
Page 212: Dma Transfer Suspension
Direct memory access controller (DMA) RM0402 to-memory) all the remaining data have been flushed from the FIFO into the memory. • In Peripheral flow controller mode: – The last external burst or single request has been generated from the peripheral and (when the DMA is operating in peripheral-to-memory mode) the remaining data have been transferred from the FIFO into the memory –...
Page 213: Flow Controller
RM0402 Direct memory access controller (DMA) 9.3.16 Flow controller The entity that controls the number of data to be transferred is known as the flow controller. This flow controller is configured independently for each stream using the PFCTRL bit in the DMA_SxCR register.
Page 214: Summary Of The Possible Dma Configurations
Direct memory access controller (DMA) RM0402 9.3.17 Summary of the possible DMA configurations The table below summarizes the different possible DMA configurations. The forbidden configurations are highlighted in gray in the table. Table 37. Possible DMA configurations DMA transfer Flow Circular Transfer Direct...
Page 215: Error Management
RM0402 Direct memory access controller (DMA) Configure the data transfer direction, peripheral and memory incremented/fixed mode, single or burst transactions, peripheral and memory data widths, circular mode, double-buffer mode and interrupts after half and/or full transfer, and/or errors in the DMA_SxCR register.
Page 216: Dma Interrupts
Direct memory access controller (DMA) RM0402 If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO threshold level, the faulty stream is automatically disabled through a hardware clear of its EN bit in the corresponding stream configuration register (DMA_SxCR). If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register.
Page 217: Dma Registers
RM0402 Direct memory access controller (DMA) DMA registers The DMA registers have to be accessed by words (32 bits). 9.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res.
Page 218: Dma High Interrupt Status Register (Dma_Hisr)
Direct memory access controller (DMA) RM0402 9.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5...
Page 219: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
RM0402 Direct memory access controller (DMA) 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x008 Reset value: 0x0000 0000 Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res. CFEIF2 Res. Res. Res. Res.
Page 220: Dma Stream X Configuration Register (Dma_Sxcr)
Direct memory access controller (DMA) RM0402 Bits 24, 18, 8, 2 CDMEIFx: stream x clear direct mode error interrupt flag (x = 7 to 4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register. Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: stream x clear FIFO error interrupt flag (x = 7 to 4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
Page 221 RM0402 Direct memory access controller (DMA) Bit 20 Reserved, must be kept at reset value. Bit 19 CT: current target (only in double-buffer mode) This bit is set and cleared by hardware. It can also be written by software. 0: current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer) 1: current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer) This bit can be written only if EN = 0 to indicate the target memory area of the first transfer.
Page 222 Direct memory access controller (DMA) RM0402 Bit 10 MINC: memory increment mode This bit is set and cleared by software. 0: memory address pointer is fixed 1: memory address pointer is incremented after each data transfer (increment is done according to MSIZE) This bit is protected and can be written only if EN = 0.
Page 223: Dma Stream X Number Of Data Register (Dma_Sxndtr)
RM0402 Direct memory access controller (DMA) Bit 1 DMEIE: direct mode error interrupt enable This bit is set and cleared by software. 0: DME interrupt disabled 1: DME interrupt enabled Bit 0 EN: stream enable / flag stream ready when read low This bit is set and cleared by software.
Page 224: Dma Stream X Peripheral Address Register (Dma_Sxpar)
Direct memory access controller (DMA) RM0402 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) Address offset: 0x018 + 0x018 * x, (x = 0 to 7) Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: peripheral address Base address of the peripheral data register from/to which the data is read/written. These bits are write-protected and can be written only when bit EN = 0 in DMA_SxCR.
Page 225: Dma Stream X Fifo Control Register (Dma_Sxfcr)
RM0402 Direct memory access controller (DMA) Bits 31:0 M1A[31:0]: memory 1 address (used in case of double-buffer mode) Base address of memory area 1 from/to which the data is read/written. This register is used only for the double-buffer mode. These bits are write-protected. They can be written only if: –...
Page 226 Direct memory access controller (DMA) RM0402 Bits 1:0 FTH[1:0]: FIFO threshold selection These bits are set and cleared by software. 00: 1/4 full FIFO 01: 1/2 full FIFO 10: 3/4 full FIFO 11: full FIFO These bits are not used in the direct mode when the DMIS = 0. These bits are protected and can be written only if EN = 0.
Page 227: Dma Register Map
RM0402 Direct memory access controller (DMA) 9.5.11 DMA register map Table 39. DMA register map and reset values Offset Register name DMA_LISR 0x000 Reset value DMA_HISR 0x004 Reset value DMA_LIFCR 0x008 Reset value DMA_HIFCR 0x00C Reset value DMA_S0CR 0x010 Reset value DMA_S0NDTR NDT[15:0] 0x014...
Page 228 Direct memory access controller (DMA) RM0402 Table 39. DMA register map and reset values (continued) Offset Register name DMA_S1M0AR M0A[31:0] 0x034 Reset value DMA_S1M1AR M1A[31:0] 0x038 Reset value DMA_S1FCR FS[2:0] 0x03C Reset value DMA_S2CR 0x040 Reset value DMA_S2NDTR NDT[15:0] 0x044 Reset value DMA_S2PAR PA[31:0]...
Page 229 RM0402 Direct memory access controller (DMA) Table 39. DMA register map and reset values (continued) Offset Register name DMA_S3FCR FS[2:0] 0x06C Reset value DMA_S4CR 0x070 Reset value DMA_S4NDTR NDT[15:0] 0x074 Reset value DMA_S4PAR PA[31:0] 0x078 Reset value DMA_S4M0AR M0A[31:0] 0x07C Reset value DMA_S4M1AR M1A[31:0]...
Page 230 Direct memory access controller (DMA) RM0402 Table 39. DMA register map and reset values (continued) Offset Register name DMA_S6CR 0x0A0 Reset value DMA_S6NDTR NDT[15:0] 0x0A4 Reset value DMA_S6PAR PA[31:0] 0x0A8 Reset value DMA_S6M0AR M0A[31:0] 0x0AC Reset value DMA_S6M1AR M1A[31:0] 0x0B0 Reset value DMA_S6FCR FS[2:0]...
Page 231: Interrupts And Events
RM0402 Interrupts and events Interrupts and events 10.1 Nested vectored interrupt controller (NVIC) 10.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ® • 52 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M4 with FPU) •...
Page 232: Table 40. Vector Table For Stm32F412Xx
Interrupts and events RM0402 Table 40. Vector table for STM32F412xx Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt, Clock Security fixed 0x0000 0008 System fixed HardFault All class of fault 0x0000 000C settable MemManage Memory management...
Page 233 RM0402 Interrupts and events Table 40. Vector table for STM32F412xx (continued) Type of Acronym Description Address priority settable DMA1_Stream4 DMA1 Stream4 global interrupt 0x0000 007C settable DMA1_Stream5 DMA1 Stream5 global interrupt 0x0000 0080 settable DMA1_Stream6 DMA1 Stream6 global interrupt 0x0000 0084 settable ADC1 global interrupt 0x0000 0088...
Page 234 Interrupts and events RM0402 Table 40. Vector table for STM32F412xx (continued) Type of Acronym Description Address priority EXTI Line 17 interrupt / EXTI17 / settable 0x0000 00E4 RTC Alarms (A and B) through EXTI line RTC Alarm interrupt EXTI Line 18 interrupt / USB On-The-Go FS settable EXTI18 / OTG_FS_WKUP 0x0000 00E8...
Page 235: Exti Main Features
RM0402 Interrupts and events Table 40. Vector table for STM32F412xx (continued) Type of Acronym Description Address priority settable DMA2_Stream6 DMA2 Stream6 global interrupt 0x0000 0154 settable DMA2_Stream7 DMA2 Stream7 global interrupt 0x0000 0158 settable USART6 USART6 global interrupt 0x0000 015C settable I2C3_EV C3 event interrupt...
Page 236: Exti Block Diagram
Interrupts and events RM0402 10.2.2 EXTI block diagram Figure 29 shows the block diagram. Figure 29. External interrupt/event controller block diagram AMBA APB bus PCLK2 Peripheral interface Software Rising Falling Pending Interrupt interrupt trigger trigger request mask event selection selection register register register...
Page 237: Functional Description
RM0402 Interrupts and events 10.2.4 Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated.
Page 238: External Interrupt/Event Line Mapping
Interrupts and events RM0402 10.2.5 External interrupt/event line mapping Up to STM32F412xx are connected to the 16 external interrupt/event lines in the following manner: Figure 30. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register PA15...
Page 239: Exti Registers
RM0402 Interrupts and events 10.3 registers EXTI Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 240 Interrupts and events RM0402 Bits 22:21 MR[22:21]: Event mask on line x 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked Bits 20:19 Reserved, must be kept at reset value. Bits 18:0 MR[18:0]: Event mask on line x 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked 240/1163...
Page 241: Rising Trigger Selection Register (Exti_Rtsr)
RM0402 Interrupts and events 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 TR[22:21]: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line...
Page 242: Falling Trigger Selection Register (Exti_Ftsr)
Interrupts and events RM0402 10.3.4 Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 TR[22:21]: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line.
Page 243: Software Interrupt Event Register (Exti_Swier)
RM0402 Interrupts and events 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER...
Page 244: Pending Register (Exti_Pr)
Interrupts and events RM0402 10.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. PR22 PR21 Res. Res. PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PR15 PR14 PR13 PR12 PR11 PR10 rc_w1 rc_w1...
Page 245: Exti Register Map
RM0402 Interrupts and events 10.3.7 EXTI register map Table 41 gives the EXTI register map and the reset values. Table 41. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] [22:21] 0x00 Reset value EXTI_EMR MR[18:0] [22:21] 0x04 Reset value EXTI_RTSR...
Page 246: Flexible Static Memory Controller (Fsmc)
Flexible static memory controller (FSMC) RM0402 Flexible static memory controller (FSMC) 11.1 Introduction The flexible static memory controller (FSMC) includes one memory controller: • The NOR/PSRAM memory controller 11.2 FSMC main features The FSMC functional block makes the interface with: synchronous and asynchronous static memories.
Page 247: Fmc Block Diagram
RM0402 Flexible static memory controller (FSMC) The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time. 11.3 FMC block diagram The FSMC consists of the following main blocks:...
Page 248: Ahb Interface
Flexible static memory controller (FSMC) RM0402 11.4 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 249: External Device Address Mapping
RM0402 Flexible static memory controller (FSMC) transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in Linear burst mode of undefined length.
Page 250: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0402 1. HADDR are internal AHB address lines that are translated to external memory. The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.
Page 251: External Memory Interface Signals
RM0402 Flexible static memory controller (FSMC) and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1 register: • If the CCLKEN bit is reset, the FSMC generates the clock (CLK) only during synchronous accesses (Read/write transactions). • If the CCLKEN bit is set, the FSMC generates a continuous clock during asynchronous and synchronous accesses.
Page 252: Table 45. Non-Multiplexed I/O Nor Flash Memory
Flexible static memory controller (FSMC) RM0402 NOR Flash memory, non-multiplexed I/Os Table 45. Non-multiplexed I/O NOR Flash memory FSMC signal name Function Clock (for synchronous access) A[25:0] Address bus D[15:0] Bidirectional data bus NE[x] Chip select, x = 1..4 Output enable Write enable Latch enable (this signal is called address NL(=NADV)
Page 253: Supported Memories And Transactions
RM0402 Flexible static memory controller (FSMC) Table 47. Non-multiplexed I/Os PSRAM/SRAM (continued) FSMC signal Function name NE[x] Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid only for PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FSMC NBL[1:0]...
Page 254: Table 49. Nor Flash/Psram: Example Of Supported Memories
Flexible static memory controller (FSMC) RM0402 Table 49. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Asynchronous Asynchronous NOR Flash Asynchronous Split into 2 FSMC accesses (muxed I/Os Asynchronous Split into 2 FSMC accesses and nonmuxed...
Page 255: General Timing Rules
RM0402 Flexible static memory controller (FSMC) 11.6.3 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In Synchronous mode (read or write), all output signals change on the rising edge of HCLK.
Page 256: Figure 33. Mode 1 Read Access Waveforms
Flexible static memory controller (FSMC) RM0402 Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers. Figure 33. Mode 1 read access waveforms Memory transaction A[25:0] NBL[1:0]...
Page 257: Table 50. Fsmc_Bcrx Bitfields (Mode 1)
RM0402 Flexible static memory controller (FSMC) The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). Table 50.
Page 258: Figure 35. Mode A Read Access Waveforms
Flexible static memory controller (FSMC) RM0402 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 35. Mode A read access waveforms Memory transaction A[25:0] NBL[1:0] High data driven D[15:0] by memory ADDSET DATAST HCLK cycles HCLK cycles MS34479V1 1. NBL[1:0] are driven low during the read access Figure 36.
Page 259: Table 52. Fsmc_Bcrx Bitfields (Mode A)
RM0402 Flexible static memory controller (FSMC) The differences compared with Mode 1 are the toggling of NOE and the independent read and write timings. Table 52. FSMC_BCRx bitfields (mode A) Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN...
Page 260: Table 54. Fsmc_Bwtrx Bitfields (Mode A)
Flexible static memory controller (FSMC) RM0402 Table 54. FSMC_BWTRx bitfields (mode A) Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST HCLK cycles) for write 15:8 DATAST...
Page 261: Figure 38. Mode 2 Write Access Waveforms
RM0402 Flexible static memory controller (FSMC) Figure 38. Mode 2 write access waveforms Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FMC ADDSET (DATAST + 1) HCLK cycles HCLK cycles MS34482V2 Figure 39. Mode B write access waveforms Memory transaction A[25:0] NADV 1HCLK...
Page 262: Table 55. Fsmc_Bcrx Bitfields (Mode 2/B)
Flexible static memory controller (FSMC) RM0402 Table 55. FSMC_BCRx bitfields (mode 2/B) Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in Asynchronous mode) 18:16 CPSIZE 0x0 (no effect in Asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature.
Page 263: Table 57. Fsmc_Bwtrx Bitfields (Mode 2/B)
RM0402 Flexible static memory controller (FSMC) Table 57. FSMC_BWTRx bitfields (mode 2/B) Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 0x1 if Extended mode is set 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the access second phase (DATAST HCLK cycles) for 15:8 DATAST...
Page 264: Table 58. Fsmc_Bcrx Bitfields (Mode C)
Flexible static memory controller (FSMC) RM0402 Figure 41. Mode C write access waveforms Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC ADDSET (DATAST + 1) HCLK cycles HCLK cycles MS34485V1 The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.
Page 265: Table 59. Fsmc_Btrx Bitfields (Mode C)
RM0402 Flexible static memory controller (FSMC) Table 58. FSMC_BCRx bitfields (mode C) (continued) Bit number Bit name Value to set MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 59. FSMC_BTRx bitfields (mode C) Bit number Bit name Value to set 31:30 Reserved 29:28...
Page 266: Figure 42. Mode D Read Access Waveforms
Flexible static memory controller (FSMC) RM0402 Mode D - asynchronous access with extended address Figure 42. Mode D read access waveforms Memory transaction A[25:0] NADV High data driven D[15:0] by memory ADDSET DATAST HCLK cycles HCLK cycles ADDHLD HCLK cycles MS34486V1 Figure 43.
Page 267: Table 61. Fsmc_Bcrx Bitfields (Mode D)
RM0402 Flexible static memory controller (FSMC) The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 61. FSMC_BCRx bitfields (mode D) Bit number Bit name Value to set 31:22 Reserved...
Page 268: Table 63. Fsmc_Bwtrx Bitfields (Mode D)
Flexible static memory controller (FSMC) RM0402 Table 63. FSMC_BWTRx bitfields (mode D) Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST + 1 HCLK cycles) for 15:8 DATAST...
Page 269: Table 64. Fsmc_Bcrx Bitfields (Muxed Mode)
RM0402 Flexible static memory controller (FSMC) Figure 45. Muxed write access waveforms Memory transaction A[25:16] NADV 1HCLK AD[15:0] Lower address data driven by FSMC ADDSET ADDHLD (DATAST + 1) HCLK cycles HCLK cycles HCLK cycles MSv40112V2 The difference with mode D is the drive of the lower address byte(s) on the data bus. Table 64.
Page 270: Table 65. Fsmc_Btrx Bitfields (Muxed Mode)
Flexible static memory controller (FSMC) RM0402 Table 64. FSMC_BCRx bitfields (Muxed mode) (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 65. FSMC_BTRx bitfields (Muxed mode) Bit number Bit name Value to set 31:30 Reserved 29:28...
Page 271: Figure 46. Asynchronous Wait During A Read Access Waveforms
RM0402 Flexible static memory controller (FSMC) The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: –...
Page 272: Synchronous Transactions
Flexible static memory controller (FSMC) RM0402 Figure 47. Asynchronous wait during a write access waveforms Memory transaction A[25:0] address phase data setup phase NWAIT don’t care don’t care 1HCLK D[15:0] data driven by FSMC 3HCLK MS30464V2 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. 11.6.5 Synchronous transactions The memory clock, FSMC_CLK, is a submultiple of HCLK.
Page 273 RM0402 Flexible static memory controller (FSMC) Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FSMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 274: Figure 48. Wait Configuration Waveforms
Flexible static memory controller (FSMC) RM0402 Figure 48. Wait configuration waveforms Memory transaction = burst of 4 half words HCLK addr[25:16] A[25:16] NADV NWAIT (WAITCFG = 0) NWAIT (WAITCFG = 1) inserted wait state addr[15:0] data data data A/D[15:0] ai15798c 274/1163 RM0402 Rev 6...
Page 275: Table 66. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Read Mode)
RM0402 Flexible static memory controller (FSMC) Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG= (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 276: Table 67. Fsmc_Btrx Bitfields (Synchronous Multiplexed Read Mode)
Flexible static memory controller (FSMC) RM0402 Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode) (continued) Bit number Bit name Value to set WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP...
Page 277: Figure 50. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram)
RM0402 Flexible static memory controller (FSMC) Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) Memory transaction = burst of 2 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 278: Table 68. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Write Mode)
Flexible static memory controller (FSMC) RM0402 Table 68. FSMC_BCRx bitfields (Synchronous multiplexed write mode) (continued) Bit number Bit name Value to set WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed...
Page 279: Nor/Psram Controller Registers
RM0402 Flexible static memory controller (FSMC) 11.6.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control register for bank x (FSMC_BCRx) (x = 1 to 4) Address offset: 8 * (x – 1), (x = 1 to 4) Reset value: Bank 1: 0x0000 30DB Reset value: Bank 2: 0x0000 30D2 Reset value: Bank 3: 0x0000 30D2 Reset value: Bank 4: 0x0000 30D2...
Page 280 Flexible static memory controller (FSMC) RM0402 Bit 19 CBURSTRW: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register.
Page 281 RM0402 Flexible static memory controller (FSMC) Bit 9 WAITPOL: Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode. 0: NWAIT active low (default after reset) 1: NWAIT active high Bit 8 BURSTEN: Burst enable bit This bit enables/disables synchronous accesses during read operations.
Page 282 Flexible static memory controller (FSMC) RM0402 one to configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx registers). Res. Res. ACCMOD[1:0] DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams.
Page 283 RM0402 Flexible static memory controller (FSMC) Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
Page 284 Flexible static memory controller (FSMC) RM0402 Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 33 Figure 45), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
Page 285 RM0402 Flexible static memory controller (FSMC) Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: Access mode A 01: Access mode B 10: Access mode C 11: Access mode D...
Page 286: Fsmc Register Map
Flexible static memory controller (FSMC) RM0402 Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 33 Figure 45), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
Page 287 RM0402 Flexible static memory controller (FSMC) Table 70. FSMC register map and reset values (continued) Offset Register BUSTURN[3:0 FSMC_BTR4 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x1C Reset value BUSTURN[3:0 FSMC_BWTR1 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x104 Reset value BUSTURN[3:0 FSMC_BWTR2 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x10C Reset value BUSTURN...
Page 288: Quad-Spi Interface (Quadspi)
Quad-SPI interface (QUADSPI) RM0402 Quad-SPI interface (QUADSPI) 12.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 289: Quadspi Pins
RM0402 Quad-SPI interface (QUADSPI) Figure 52. QUADSPI block diagram when dual-flash mode is enabled QUADSPI Registers / Clock control management SPI FLASH 1 BK1_IO0/SO Q0/SI BK1_IO1/SI Q1/SO BK1_IO2 FIFO Q2/WP BK1_IO3 Q3/HOLD BK1_nCS SPI FLASH 2 Shift register BK2_IO0/SO Q0/SI BK2_IO1/SI Q1/SO BK2_IO2...
Page 290: Quadspi Command Sequence
Quad-SPI interface (QUADSPI) RM0402 12.3.3 QUADSPI command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present.
Page 291 RM0402 Quad-SPI interface (QUADSPI) Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
Page 292: Quadspi Signal Interface Protocol Modes
Quad-SPI interface (QUADSPI) RM0402 mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode.
Page 293: Figure 54. An Example Of A Ddr Command In Quad Mode
RM0402 Quad-SPI interface (QUADSPI) SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge.
Page 294: Quadspi Indirect Mode
Quad-SPI interface (QUADSPI) RM0402 The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2.
Page 295 RM0402 Quad-SPI interface (QUADSPI) is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command.
Page 296: Quadspi Status Flag Polling Mode
Quad-SPI interface (QUADSPI) RM0402 12.3.6 QUADSPI status flag polling mode In automatic-polling mode, the QUADSPI periodically starts a command to read a defined number of status bytes (up to 4). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.
Page 297: Quadspi Flash Memory Configuration
RM0402 Quad-SPI interface (QUADSPI) By default, the QUADSPI never stops its prefetch operation, keeping the previous read operation active with nCS maintained low, even if no access to the Flash memory occurs for a long time. Since Flash memories tend to consume more when nCS is held low, the application might want to activate the timeout counter (TCEN = 1, bit 3 of QUADSPI_CR) so that nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data.
Page 298: Quadspi Usage
Quad-SPI interface (QUADSPI) RM0402 The QUADSPI is configured using the QUADSPI_CR. The user shall configure the clock prescaler division factor and the sample shifting settings for the incoming data. DDR mode can be set through the DDRM bit. When setting QUADSPI interface in DDR mode, the internal divider of kernel clock must be set with a division ratio of 2 or more.
Page 299 RM0402 Quad-SPI interface (QUADSPI) When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) •...
Page 300: Sending The Instruction Only Once
Quad-SPI interface (QUADSPI) RM0402 In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses.
Page 301: Ncs Behavior
RM0402 Quad-SPI interface (QUADSPI) In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty. In automatic-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1, or due to an abort.
Page 302: Quadspi Interrupts
Quad-SPI interface (QUADSPI) RM0402 Figure 57. nCS when CKMODE = 1 in DDR mode (T = CLK period) SCLK MS35321V1 When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation, the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs when an operation is stalled, nCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later, as shown in Figure...
Page 303: Table 72. Quadspi Interrupt Requests
RM0402 Quad-SPI interface (QUADSPI) Table 72. QUADSPI interrupt requests Interrupt event Event flag Enable control bit Timeout TOIE Status match SMIE FIFO threshold FTIE Transfer complete TCIE Transfer error TEIE RM0402 Rev 6 303/1163...
Page 304: Quadspi Registers
Quad-SPI interface (QUADSPI) RM0402 12.5 QUADSPI registers 12.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER[7:0] APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. FTHRES[4:0] FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31:24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1).
Page 305 RM0402 Quad-SPI interface (QUADSPI) Bit 19 SMIE: Status match interrupt enable This bit enables the status match interrupt. 0: Interrupt disable 1: Interrupt enabled Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt.
Page 306 Quad-SPI interface (QUADSPI) RM0402 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data to be sampled later in order to account for external signal delays.
Page 307: Quadspi Device Configuration Register (Quadspi_Dcr)
RM0402 Quad-SPI interface (QUADSPI) 12.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE[4:0] Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. Res.
Page 308: Quadspi Status Register (Quadspi_Sr)
Quad-SPI interface (QUADSPI) RM0402 12.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[5:0] Res. Res. BUSY Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 FLEVEL[5:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO.
Page 309: Quadspi Flag Clear Register (Quadspi_Fcr)
RM0402 Quad-SPI interface (QUADSPI) 12.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 310: Quadspi Communication Configuration Register (Quadspi_Ccr)
Quad-SPI interface (QUADSPI) RM0402 Bits 31:0 DL[31:0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI continues until the end of memory, as defined by FSIZE.
Page 311 RM0402 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode Section 12.3.12: Sending the instruction only once on page 300. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 312: Quadspi Address Register (Quadspi_Ar)
Quad-SPI interface (QUADSPI) RM0402 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 313: Quadspi Alternate Bytes Registers (Quadspi_Abr)
RM0402 Quad-SPI interface (QUADSPI) 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31:0 ALTERNATE[31:0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 12.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020...
Page 314: Quadspi Polling Status Mask Register (Quadspi_Psmkr)
Quad-SPI interface (QUADSPI) RM0402 12.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31:0 MASK[31:0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is...
Page 315: Quadspi Polling Interval Register (Quadspi_Pir)
RM0402 Quad-SPI interface (QUADSPI) 12.5.12 QUADSPI polling interval register (QUADSPI_PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 INTERVAL[15:0]: Polling interval Number of CLK cycles between to read during automatic polling phases.
Page 316: Quadspi Register Map
Quad-SPI interface (QUADSPI) RM0402 12.5.14 QUADSPI register map Table 73. QUADSPI register map and reset values Register Offset name FTHRES QUADSPI_CR PRESCALER[7:0] [4:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[5:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 317: Analog-To-Digital Converter (Adc)
RM0402 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 13.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel.
Page 318: Figure 59. Single Adc Block Diagram
Analog-to-digital converter (ADC) RM0402 Figure 59. Single ADC block diagram Interrupt Flags enable bits DMA overrun OVRIE End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE Analog watchdog event AWDIE Analog watchdog Compare result Higher threshold (12 bits) Lower threshold (12 bits) Injected data registers V REF+...
Page 319: Adc On-Off Control
RM0402 Analog-to-digital converter (ADC) Table 74. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ positive 1.8 V ≤ V ≤ V REF+ Analog power supply equal to V Input, analog supply 2.4 V ≤V ≤V (3.6 V) for full speed...
Page 320: Single Conversion Mode
Analog-to-digital converter (ADC) RM0402 The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen group.
Page 321: Timing Diagram
RM0402 Analog-to-digital converter (ADC) Note: Injected channels cannot be converted continuously. The only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using JAUTO bit), refer to Auto-injection section) 13.3.6 Timing diagram As shown in Figure 60, the ADC needs a stabilization time of t...
Page 322: Scan Mode
Analog-to-digital converter (ADC) RM0402 Figure 61. Analog watchdog’s guarded area Analog voltage Higher threshold Guarded area Lower threshold ai16048 Table 75. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None...
Page 323: Injected Channel Management
RM0402 Analog-to-digital converter (ADC) 13.3.9 Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register. Start the conversion of a group of regular channels either by external trigger or by setting the SWSTART bit in the ADC_CR2 register. If an external injected trigger occurs or if the JSWSTART bit is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches to Scan-once mode.
Page 324: Discontinuous Mode
Analog-to-digital converter (ADC) RM0402 13.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADC_SQRx registers.
Page 325: Data Alignment
RM0402 Analog-to-digital converter (ADC) 13.4 Data alignment The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after conversion. Data can be right- or left-aligned as shown in Figure 63 Figure The converted data value from the injected group of channels is decreased by the user- defined offset written in the ADC_JOFRx registers so the result can be a negative value.
Page 326: Channel-Wise Programmable Sampling Time
Analog-to-digital converter (ADC) RM0402 13.5 Channel-wise programmable sampling time The ADC samples the input voltage for a number of ADCCLK cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sampling time. The total conversion time is calculated as follows: = Sampling time + 12 cycles conv...
Page 327: Table 77. External Trigger For Regular Channels
RM0402 Analog-to-digital converter (ADC) Table 77. External trigger for regular channels Source Type EXTSEL[3:0] TIM1_CH1 event 0000 TIM1_CH2 event 0001 TIM1_CH3 event 0010 TIM2_CH2 event 0011 TIM2_CH3 event 0100 TIM2_CH4 event 0101 TIM2_TRGO event 0110 TIM3_CH1 event Internal signal from on-chip timers 0111 TIM3_TRGO event 1000...
Page 328: Fast Conversion Mode
Analog-to-digital converter (ADC) RM0402 Table 78 gives the possible external trigger for injected conversion. Table 78. External trigger for injected channels Source Connection type JEXTSEL[3:0] TIM1_CH4 event 0000 TIM1_TRGO event 0001 TIM2_CH1 event 0010 TIM2_TRGO event 0011 TIM3_CH2 event 0100 TIM3_CH4 event 0101 TIM4_CH1 event...
Page 329: Data Management
RM0402 Analog-to-digital converter (ADC) 13.8 Data management 13.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register.
Page 330: Conversions Without Dma And Without Overrun Detection
Analog-to-digital converter (ADC) RM0402 13.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0).
Page 331: Battery Charge Monitoring
RM0402 Analog-to-digital converter (ADC) Reading the temperature To use the sensor: Select ADC1_IN18 input channel. Select a sampling time greater than the minimum sampling time specified in the datasheet. Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor from power down mode Start the ADC conversion by setting the SWSTART bit (or by external trigger) Read the resulting V...
Page 332: Adc Interrupts
Analog-to-digital converter (ADC) RM0402 13.11 ADC interrupts An interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. Separate interrupt enable bits are available for flexibility. Two other flags are present in the ADC_SR register, but there is no interrupt associated with them: •...
Page 333: Adc Registers
RM0402 Analog-to-digital converter (ADC) 13.12 ADC registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 13.12.1 ADC status register (ADC_SR) Address offset: 0x00...
Page 334: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0402 13.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. OVRIE AWDEN JAWDEN Res. Res. Res. Res. Res. Res. DISCNUM[2:0] JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value.
Page 335 RM0402 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
Page 336: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0402 13.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 Res. SWSTART EXTEN EXTSEL[3:0] Res. JSWSTART JEXTEN JEXTSEL[3:0] Res. Res. Res. Res. ALIGN EOCS Res. Res. Res. Res. Res. Res. CONT ADON Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts.
Page 337 RM0402 Analog-to-digital converter (ADC) Bit 22 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by hardware as soon as the conversion starts. 0: Reset state 1: Starts conversion of injected channels This bit can be set only when ADON = 1 otherwise no conversion is launched. Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group.
Page 338: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0402 Bit 8 DMA: Direct memory access mode (for single ADC mode) This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Bits 7:2 Reserved, must be kept at reset value.
Page 339: Adc Sample Time Register 2 (Adc_Smpr2)
RM0402 Analog-to-digital converter (ADC) 13.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] SMP5_0 SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 340: Adc Watchdog Lower Threshold Register (Adc_Ltr)
Analog-to-digital converter (ADC) RM0402 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HT[11:0] Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog higher threshold These bits are written by software to define the higher threshold for the analog watchdog.
Page 341: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0402 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence...
Page 342: Adc Regular Sequence Register 3 (Adc_Sqr3)
Analog-to-digital converter (ADC) RM0402 13.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. SQ6[4:0] SQ5[4:0] SQ4[4:1] SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 6th in the sequence to be converted.
Page 343: Adc Injected Sequence Register (Adc_Jsqr)
RM0402 Analog-to-digital converter (ADC) 13.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JL[1:0] JSQ4[4:1] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 344: Adc Regular Data Register (Adc_Dr)
Analog-to-digital converter (ADC) RM0402 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 63 Figure 13.12.14 ADC regular data register (ADC_DR)
Page 345: Adc Common Control Register (Adc_Ccr)
RM0402 Analog-to-digital converter (ADC) Bit 2 JEOC1: Injected channel end of conversion of ADC1 This bit is a copy of the JEOC bit in the ADC1_SR register. Bit 1 EOC1: End of conversion of ADC1 This bit is a copy of the EOC bit in the ADC1_SR register. Bit 0 AWD1: Analog watchdog flag of ADC1 This bit is a copy of the AWD bit in the ADC1_SR register.
Page 346: Adc Register Map
Analog-to-digital converter (ADC) RM0402 13.13 ADC register map The following table summarizes the ADC registers. Table 80. ADC global register map Offset Register 0x000 - 0x04C ADC1 0x050 - 0x2FC Reserved 0x300 - 0x308 Common registers Table 81. ADC register map and reset values Offset Register ADC_SR...
Page 347: Table 82. Adc Register Map And Reset Values (Common Adc Registers)
RM0402 Analog-to-digital converter (ADC) Table 81. ADC register map and reset values (continued) Offset Register ADC_SQR3 Regular channel sequence SQx_x bits 0x34 Reset value ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits 0x38 Reset value ADC_JDR1 JDATA[15:0] 0x3C Reset value ADC_JDR2 JDATA[15:0] 0x40 Reset value...
Page 348: Digital Filter For Sigma Delta Modulators (Dfsdm)
Digital filter for sigma delta modulators (DFSDM) RM0402 Digital filter for sigma delta modulators (DFSDM) 14.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators. It is featuring up to 4 external digital serial interfaces (channels) and up to 2 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution.
Page 349: Dfsdm Main Features
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.2 DFSDM main features • Up to 4 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) •...
Page 350: Dfsdm Implementation
Digital filter for sigma delta modulators (DFSDM) RM0402 14.3 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 83. DFSDM1 implementation DFSDM features DFSDM1 Number of channels Number of filters Input from internal ADC Supported trigger sources Pulses skipper ID registers support 1.
Page 351: Dfsdm Functional Description
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.4 DFSDM functional description 14.4.1 DFSDM block diagram Figure 67. Single DFSDM block diagram APB bus Sample 1 Sample 0 Parallel input data register 0 Sample 1 Sample 0 Parallel input data register 3 EXTRG[1:0] Data 0...
Page 352: Dfsdm Pins And Internal Signals
Digital filter for sigma delta modulators (DFSDM) RM0402 1. This example shows 2 DFSDM filters and 4 input channels. 14.4.2 DFSDM pins and internal signals Table 84. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply. Power supply Digital ground power supply.
Page 353: Dfsdm Reset And Clocks
RM0402 Digital filter for sigma delta modulators (DFSDM) Table 87. DFSDM break connection Break name Break destination dfsdm_break[0] TIM1 break dfsdm_break[1] dfsdm_break[2] TIM8 break dfsdm_break[3] 14.4.3 DFSDM reset and clocks DFSDM on-off control The DFSDM interface is globally enabled by setting DFSDMEN=1 in the DFSDM_CH0CFGR1 register.
Page 354: Serial Channel Transceivers
Digital filter for sigma delta modulators (DFSDM) RM0402 clock selected by SAI1SEL[1:0] field in RCC configuration (see Section 6.3.24: RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)). 14.4.4 Serial channel transceivers There are 4 multiplexed serial data channels which can be selected for conversion by each filter or Analog watchdog or Short-circuit detector.
Page 355: Figure 68. Input Channel Pins Redirection
RM0402 Digital filter for sigma delta modulators (DFSDM) Figure 68. Input channel pins redirection (. . .) CH(y Decode DATIN(y CKIN(y FLT(x Decode DATINy CKINy FLT(x+1) FLTx CH(y-1) Decode DATIN(y-1) CKIN(y-1) FLT0 Decode DATAIN0 CKIN0 (. . .) MSv41632V1 Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆...
Page 356 Digital filter for sigma delta modulators (DFSDM) RM0402 SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source.
Page 357: Figure 69. Channel Transceiver Timing Diagrams
RM0402 Digital filter for sigma delta modulators (DFSDM) Figure 69. Channel transceiver timing diagrams (SPICKSEL=0) SITP = 00 SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 SITP = 0 SITP = 1 SITP = 2 SITP = 3 recovered clock recovered data MS30766V3 RM0402 Rev 6 357/1163...
Page 358: Figure 70. Clock Absence Timing Diagram For Spi
Digital filter for sigma delta modulators (DFSDM) RM0402 Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register.
Page 359: Figure 71. Clock Absence Timing Diagram For Manchester Coding
RM0402 Digital filter for sigma delta modulators (DFSDM) The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 360 Digital filter for sigma delta modulators (DFSDM) RM0402 Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:...
Page 361: Figure 72. First Conversion For Manchester Coding (Manchester Synchronization)
RM0402 Digital filter for sigma delta modulators (DFSDM) Figure 72. First conversion for Manchester coding (Manchester synchronization) SITP = 2 SITP = 3 recovered clock data from modulator CHEN real start of first conversion first conversion start trigger first data bit toggle - end of Manchester synchronization recovered data CKABF[y] clearing of CKABF[y] flag by software polling...
Page 362 Digital filter for sigma delta modulators (DFSDM) RM0402 Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1):...
Page 363: Configuring The Input Serial Interface
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.4.5 Configuring the input serial interface The following parameters must be configured for the input serial interface: • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in DFSDM_CH0CFGR1 register.
Page 364: Figure 73. Dfsdm_Chydatinr Registers Operation Modes And Assignment
Digital filter for sigma delta modulators (DFSDM) RM0402 address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading.
Page 365: Channel Selection
RM0402 Digital filter for sigma delta modulators (DFSDM) The write into DFSDM_CHyDATINR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y). Otherwise written data are lost for next processing. For example: for single conversion and interleaved mode, do not start writing pair of data samples into DFSDM_CHyDATINR before the single conversion is started (any data present in the DFSDM_CHyDATINR before starting a conversion is discarded).
Page 366: Figure 74. Example: Sinc3 Filter Response
Digital filter for sigma delta modulators (DFSDM) RM0402 reach the required output data rates and required output data resolution. The configurable parameters are: • Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register): – FastSinc – Sinc – Sinc – Sinc –...
Page 367: Integrator Unit
RM0402 Digital filter for sigma delta modulators (DFSDM) Table 88. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x +/- x +/- 2x +/- x +/- x +/- x +/- 4 +/- 16...
Page 368 Digital filter for sigma delta modulators (DFSDM) RM0402 Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0).
Page 369 RM0402 Digital filter for sigma delta modulators (DFSDM) AWHTF[3:0], AWLTF[3:0] of DFSDM_FLTxAWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[3:0] = 0x0F). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog feature at this input clock speed.
Page 370: Short-Circuit Detector
Digital filter for sigma delta modulators (DFSDM) RM0402 14.4.11 Short-circuit detector The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time.
Page 371: Data Unit Block
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.4.13 Data unit block The data unit block is the last block of the whole processing path: External Σ∆ modulators - Serial transceivers - Sinc filter - Integrator - Data unit block. The output data rate depends on the serial data stream rate, and filter and integrator settings.
Page 372: Signed Data Format
Digital filter for sigma delta modulators (DFSDM) RM0402 Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate ) must be limited to be able to read all output data: DATAIN_RATE ≤ f DATAIN_RATE where f is the bus frequency to which the DFSDM peripheral is connected.
Page 373: Continuous And Fast Continuous Modes
RM0402 Digital filter for sigma delta modulators (DFSDM) already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress.
Page 374: Power Optimization In Run Mode
Digital filter for sigma delta modulators (DFSDM) RM0402 An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register). Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’...
Page 375: Table 90. Dfsdm Interrupt Requests
RM0402 Digital filter for sigma delta modulators (DFSDM) – enabled by JOVRIE bit in DFSDM_FLTxCR2 register – indicated in JOVRF bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register • Data overrun interrupt for regular conversions: –...
Page 376: Dfsdm Dma Transfer
Digital filter for sigma delta modulators (DFSDM) RM0402 Table 90. DFSDM interrupt requests (continued) Event/Interrupt clearing Interrupt enable Interrupt event Event flag method control bit Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE AWDF, writing CLRAWHTF[3:0] = 1 AWDIE, Analog watchdog AWHTF[3:0], writing CLRAWLTF[3:0] = 1...
Page 377 RM0402 Digital filter for sigma delta modulators (DFSDM) Bit 31 DFSDMEN: Global enable for DFSDM interface 0: DFSDM interface disabled 1: DFSDM interface enabled If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
Page 378 Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y 0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 1: Reserved 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
Page 379: Dfsdm Channel Y Configuration Register (Dfsdm_Chycfgr2)
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) This register specifies the parameters used by channel y. Address offset: 0x04 + 0x20 * y, (y = 0 to 3) Reset value: 0x0000 0000 OFFSET[23:8] OFFSET[7:0] DTRBS[4:0]...
Page 380: Dfsdm Channel Y Watchdog Filter Data Register (Dfsdm_Chywdatr)
Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type –...
Page 381: Dfsdm Channel Y Data Input Register (Dfsdm_Chydatinr)
RM0402 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 WDATA[15:0]: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).
Page 382: Dfsdm Filter X Module Registers (X=0
Digital filter for sigma delta modulators (DFSDM) RM0402 14.8 DFSDM filter x module registers (x=0..1) Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR register. 14.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) Address offset: 0x100 + 0x80 * x, (x = 0 to 1) Reset value: 0x0000 0000 RDMA RCON...
Page 383 RM0402 Digital filter for sigma delta modulators (DFSDM) Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Page 384: Dfsdm Filter X Control Register 2 (Dfsdm_Fltxcr2)
Digital filter for sigma delta modulators (DFSDM) RM0402 Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group 0: The DMA channel is not enabled to read injected data 1: The DMA channel is enabled to read injected data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Page 385 RM0402 Digital filter for sigma delta modulators (DFSDM) Bits 31:20 Reserved, must be kept at reset value. Bits 19:16 AWDCH[3:0]: Analog watchdog channel selection These bits select the input channel to be guarded continuously by the analog watchdog. AWDCH[y] = 0: Analog watchdog is disabled on channel y AWDCH[y] = 1: Analog watchdog is enabled on channel y Bits 15:12 Reserved, must be kept at reset value.
Page 386: Dfsdm Filter X Interrupt And Status Register (Dfsdm_Fltxisr)
Digital filter for sigma delta modulators (DFSDM) RM0402 14.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) Address offset: 0x108 + 0x80 * x, (x = 0 to 1) Reset value: 0x00FF 0000 Res. Res. Res. Res. SCDF[3:0] Res. Res. Res.
Page 387: Dfsdm Filter X Interrupt Flag Clear Register (Dfsdm_Fltxicr)
RM0402 Digital filter for sigma delta modulators (DFSDM) Bit 4 AWDF: Analog watchdog 0: No Analog watchdog event occurred 1: The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers. This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[3:0] and AWLTF[3:0] in DFSDM_FLTxAWSR register (by writing ‘1’...
Page 388: Dfsdm Filter X Injected Channel Group Selection Register (Dfsdm_Fltxjchgr)
Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 CLRSCDF[3:0]: Clear the short-circuit detector flag CLRSCDF[y]=0: Writing ‘0’ has no effect CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0) Bits 23:20 Reserved, must be kept at reset value.
Page 389: Dfsdm Filter X Control Register (Dfsdm_Fltxfcr)
RM0402 Digital filter for sigma delta modulators (DFSDM) Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 JCHG[3:0]: Injected channel group selection JCHG[y]=0: channel y is not part of the injected group JCHG[y]=1: channel y is part of the injected group If JSCAN=1, each of the selected channels is converted, one after another.
Page 390: Dfsdm Filter X Data Register For Injected Group (Dfsdm_Fltxjdatar)
Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate) 0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (F = FOSR[9:0] +1). This number is also the decimation ratio of the output data rate from filter. This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1) Note: If FOSR = 0, then the filter has no effect (filter bypass).
Page 391: Dfsdm Filter X Data Register For The Regular Channel (Dfsdm_Fltxrdatar)
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.8.8 DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) Address offset: 0x11C + 0x80 * x, (x = 0 to 1) Reset value: 0x0000 0000 RDATA[23:8] RDATA[7:0] Res. Res. Res. RPEND Res.
Page 392: Dfsdm Filter X Analog Watchdog Low Threshold Register
Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution).
Page 393: Dfsdm Filter X Analog Watchdog Status Register
RM0402 Digital filter for sigma delta modulators (DFSDM) 14.8.11 DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) Address offset: 0x128 + 0x80 * x, (x = 0 to 1) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res.
Page 394: Dfsdm Filter X Extremes Detector Maximum Register
Digital filter for sigma delta modulators (DFSDM) RM0402 Bits 11:8 CLRAWHTF[3:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 CLRAWLTF[3:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’...
Page 395: Dfsdm Filter X Conversion Timer Register (Dfsdm_Fltxcnvtimr)
RM0402 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:2 Reserved, must be kept at reset value.
Page 396: Dfsdm Register Map
Digital filter for sigma delta modulators (DFSDM) RM0402 14.8.16 DFSDM register map The following table summarizes the DFSDM registers. Table 91. DFSDM register map and reset values Register Offset name DFSDM_ CKOUTDIV[7:0] CH0CFGR1 0x00 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH0CFGR2 0x04 reset value DFSDM_...
Page 397 RM0402 Digital filter for sigma delta modulators (DFSDM) Table 91. DFSDM register map and reset values (continued) Register Offset name DFSDM_ CH2CFGR1 0x40 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH2CFGR2 0x44 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH2AWSCDR 0x48 reset value DFSDM_ WDATA[15:0] CH2WDATR...
Page 398 Digital filter for sigma delta modulators (DFSDM) RM0402 Table 91. DFSDM register map and reset values (continued) Register Offset name DFSDM_ AWDCH[3:0] EXCH[3:0] FLT0CR2 0x104 reset value DFSDM_ SCDF[3:0] CKABF[3:0] FLT0ISR 0x108 reset value DFSDM_ CLRSCDF CLRCKABF FLT0ICR [3:0] [3:0] 0x10C reset value DFSDM_...
Page 399 RM0402 Digital filter for sigma delta modulators (DFSDM) Table 91. DFSDM register map and reset values (continued) Register Offset name DFSDM_ EXMIN[23:0] FLT0EXMIN 0x134 reset value DFSDM_ CNVCNT[27:0] FLT0CNVTIMR 0x138 reset value 0x13C - Reserved 0x17C DFSDM_ FLT1CR1 0x180 reset value DFSDM_ AWDCH[3:0] EXCH[3:0]...
Page 400 Digital filter for sigma delta modulators (DFSDM) RM0402 Table 91. DFSDM register map and reset values (continued) Register Offset name DFSDM_ AWLT[23:0] BKAWL[3:0] FLT1AWLTR 0x1A4 reset value DFSDM_ AWHTF[3:0] AWLTF[3:0] FLT1AWSR 0x1A8 reset value DFSDM_ CLRAWHTF CLRAWLTF FLT1AWCFR [3:0] [3:0] 0x1AC reset value DFSDM_...
Page 401: True Random Number Generator (Rng)
RM0402 True random number generator (RNG) True random number generator (RNG) 15.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
Page 402: Rng Functional Description
True random number generator (RNG) RM0402 15.3 RNG functional description 15.3.1 RNG block diagram Figure 75 shows the RNG block diagram. Figure 75. RNG block diagram True RNG Banked Registers RNG_CR control RNG_DR data interface RNG_SR status rng_it 16-bit rng_hclk AHB clock domain Fault detection Data shift reg...
Page 403: Random Number Generation
RM0402 True random number generator (RNG) 15.3.3 Random number generation The true random number generator (RNG) delivers truly random data through its AHB interface at deterministic intervals. Within its boundary the RNG implements the entropy source model pictured on Figure 76, and provides three main functions to the application: •...
Page 404 True random number generator (RNG) RM0402 Noise source The noise source is the component that contains the non-deterministic, entropy-providing activity that is ultimately responsible for the uncertainty associated with the bitstring output by the entropy source. It is composed of: •...
Page 405: Rng Initialization
RM0402 True random number generator (RNG) Health checks This component ensures that the entire entropy source (with its noise source) starts then operates as expected, obtaining assurance that failures are caught quickly and with a high probability and reliability. The RNG implements the following health check features. Continuous health tests, running indefinitely on the output of the noise source –...
Page 406: Rng Clocking
True random number generator (RNG) RM0402 To run the RNG in polling mode following steps are recommended: Enable the random number generation by setting the RNGEN bit to “1” in the RNG_CR register. Read the RNG_SR register and check that: –...
Page 407: Rng Low-Power Usage
RM0402 True random number generator (RNG) Noise source error detection When a noise source (or seed) error occurs, the RNG stops generating random numbers and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is available in the RNG_DR register, it must not be used as it may not have enough entropy.
Page 408: Rng Entropy Source Validation
True random number generator (RNG) RM0402 15.6 RNG entropy source validation 15.6.1 Introduction In order to assess the amount of entropy available from the RNG, STMicroelectronics has tested the peripheral using NIST SP800-22 rev1a statistical tests. The results can be provided on demand or the customer can reproduce the tests.
Page 409: Rng Registers
RM0402 True random number generator (RNG) 15.7 RNG registers The RNG is associated with a control register, a data register and a status register. 15.7.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 410: Rng Status Register (Rng_Sr)
True random number generator (RNG) RM0402 15.7.2 RNG status register (RNG_SR) Address offset: 0x004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 411: Rng Data Register (Rng_Dr)
RM0402 True random number generator (RNG) 15.7.3 RNG data register (RNG_DR) Address offset: 0x008 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read this register delivers a new random value after 42 periods of RNG clock if the output FIFO is empty.
Page 412: Rng Register Map
True random number generator (RNG) RM0402 15.7.4 RNG register map Table 94 gives the RNG register map and reset values. Table 94. RNG register map and reset map Offset Register name RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0 RNG_DR RNDATA[31:0] 0x008...
Page 413: Advanced-Control Timers (Tim1&Tim8)
RM0402 Advanced-control timers (TIM1&TIM8) Advanced-control timers (TIM1&TIM8) 16.1 TIM1&TIM8 introduction The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 414: Figure 77. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0402 Figure 77. Advanced-control timer block diagram Internal clock (CK_INT) CK_TIM18 from RCC Trigger Polarity selection, ETRF controller Edge detector and Prescaler ETRP TRGO To other timers To DAC and ADC Input filter ITR0 ITR1 TRGI Slave mode ITR2 controller ITR3...
Page 415: Tim1&Tim8 Functional Description
RM0402 Advanced-control timers (TIM1&TIM8) 16.3 TIM1&TIM8 functional description 16.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 416: Figure 78. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Advanced-control timers (TIM1&TIM8) RM0402 Figure 78. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 79.
Page 417: Counter Modes
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 418: Figure 81. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timers (TIM1&TIM8) RM0402 Figure 81. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 82. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 419: Figure 84. Counter Timing Diagram, Update Event When Arpe=0
RM0402 Advanced-control timers (TIM1&TIM8) Figure 84. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 85.
Page 420 Advanced-control timers (TIM1&TIM8) RM0402 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
Page 421: Figure 86. Counter Timing Diagram, Internal Clock Divided By 1
RM0402 Advanced-control timers (TIM1&TIM8) Figure 86. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 03 02 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 87. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 422: Figure 88. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0402 Figure 88. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 89. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 423: Figure 90. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0402 Advanced-control timers (TIM1&TIM8) Figure 90. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 424: Figure 91. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0402 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 425: Figure 93. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
RM0402 Advanced-control timers (TIM1&TIM8) Figure 93. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT 0034 0035 0036 0035 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31191V2 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 94.
Page 426: Repetition Counter
Advanced-control timers (TIM1&TIM8) RM0402 Figure 95. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 04 03 02 03 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register MS31193V2...
Page 427: Figure 97. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0402 Advanced-control timers (TIM1&TIM8) The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 428: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0402 16.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, Timer 1 can be configured to act as a prescaler for Timer 2.
Page 429: Figure 99. Ti2 External Clock Connection Example
RM0402 Advanced-control timers (TIM1&TIM8) Figure 99. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising TI2FP2 Edge External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0]...
Page 430: Figure 100. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1&TIM8) RM0402 Figure 100. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 431: Capture/Compare Channels
RM0402 Advanced-control timers (TIM1&TIM8) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 432: Figure 103. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1&TIM8) RM0402 Figure 103. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 433: Figure 105. Output Stage Of Capture/Compare Channel (Channels 1 To 3)
RM0402 Advanced-control timers (TIM1&TIM8) Figure 105. Output stage of capture/compare channel (channels 1 to 3) To the master mode controller ETRF Output enable ‘0’ circuit OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’...
Page 434: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0402 16.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 435: Pwm Input Mode
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 436: Output Compare Mode
Advanced-control timers (TIM1&TIM8) RM0402 To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) =>...
Page 437: Pwm Mode
RM0402 Advanced-control timers (TIM1&TIM8) Figure 108. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A 003B B200 B201 TIM1_CCR1 003A B201 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V2 16.3.10 PWM mode Pulse Width Modulation mode allows to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 438: Figure 109. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0402 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 439: Figure 110. Center-Aligned Pwm Waveforms (Arr=8)
RM0402 Advanced-control timers (TIM1&TIM8) Figure 110 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 110.
Page 440: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0402 Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
Page 441: Figure 111. Complementary Output With Dead-Time Insertion
RM0402 Advanced-control timers (TIM1&TIM8) Figure 111. Complementary output with dead-time insertion. OCxREF delay OCxN delay MS31095V1 Figure 112. Dead-time waveforms with delay greater than the negative pulse. OCxREF delay OCxN MS31096V1 Figure 113. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay...
Page 442: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0402 have both outputs at inactive level or both outputs active and complementary with dead- time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.
Page 443 RM0402 Advanced-control timers (TIM1&TIM8) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 444: Figure 114. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0402 Figure 114. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 445: Clearing The Ocxref Signal On An External Event
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 446: 6-Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0402 16.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 447: One-Pulse Mode
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 448: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0402 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 449: Table 95. Counting Direction Versus Encoder Signals
RM0402 Advanced-control timers (TIM1&TIM8) TIMx_ARR must be configured before starting. In the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 450: Figure 118. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0402 Figure 118. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down MS33107V1 Figure 119 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 119.
Page 451: Timer Input Xor Function
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 452: Figure 120. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0402 Figure 120 describes this example. Figure 120. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step ai17335b 452/1163 RM0402 Rev 6...
Page 453: Timx And External Trigger Synchronization
RM0402 Advanced-control timers (TIM1&TIM8) 16.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 454: Figure 122. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0402 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 455: Figure 123. Control Circuit In Trigger Mode
RM0402 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000).
Page 456: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0402 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –...
Page 457: Tim1&Tim8 Registers
RM0402 Advanced-control timers (TIM1&TIM8) 16.4 TIM1&TIM8 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits).
Page 458: Tim1&Tim8 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0402 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 459 RM0402 Advanced-control timers (TIM1&TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 460: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0402 Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Page 461 RM0402 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 462: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0402 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 463 RM0402 Advanced-control timers (TIM1&TIM8) Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled...
Page 464: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0402 16.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value.
Page 465: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0402 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 466 Advanced-control timers (TIM1&TIM8) RM0402 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
Page 467: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0402 Advanced-control timers (TIM1&TIM8) 16.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 468 Advanced-control timers (TIM1&TIM8) RM0402 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 469 RM0402 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 470: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0402 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events...
Page 471: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0402 Advanced-control timers (TIM1&TIM8) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 472 Advanced-control timers (TIM1&TIM8) RM0402 Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description...
Page 473 RM0402 Advanced-control timers (TIM1&TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
Page 474: Table 97. Output Control Bits For Complementary Ocx And Ocxn Channels
Advanced-control timers (TIM1&TIM8) RM0402 Table 97. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the timer) the timer) OCxN=0, OCxN_EN=0 OCx=0, OCx_EN=0...
Page 475: Tim1&Tim8 Counter (Timx_Cnt)
RM0402 Advanced-control timers (TIM1&TIM8) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 16.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 16.4.11...
Page 476: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1&TIM8) RM0402 16.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 477: Tim1&Tim8 Capture/Compare Register 2 (Timx_Ccr2)
RM0402 Advanced-control timers (TIM1&TIM8) 16.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 478: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1&TIM8) RM0402 16.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 479 RM0402 Advanced-control timers (TIM1&TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 480: Tim1&Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1&TIM8) RM0402 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 481: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0402 Advanced-control timers (TIM1&TIM8) 16.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 482: Tim1&Tim8 Register Map
Advanced-control timers (TIM1&TIM8) RM0402 16.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 98. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 483 RM0402 Advanced-control timers (TIM1&TIM8) Table 98. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reset value TIMx_DCR DBL[4:0]...
Page 484: General-Purpose Timers (Tim2 To Tim5)
General-purpose timers (TIM2 to TIM5) RM0402 General-purpose timers (TIM2 to TIM5) 17.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 485: Tim2 To Tim5 Functional Description
RM0402 General-purpose timers (TIM2 to TIM5) Figure 125. General-purpose timer block diagram Internal clock (CK_INT) TIMxCLK from RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP TIMx_ETR Input filter detector & prescaler to other timers to DAC/ADC ITR0 ITR1 Slave ITR2 TRGI...
Page 486: Figure 126. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0402 The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 487: Counter Modes
RM0402 General-purpose timers (TIM2 to TIM5) Figure 127. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register F8 F9 FA FB Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS35834V1...
Page 488: Figure 128. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0402 Figure 128. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timerclock = CK_CNT Counter register 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS35836V1 Figure 129. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT...
Page 489: Figure 131. Counter Timing Diagram, Internal Clock Divided By N
RM0402 General-purpose timers (TIM2 to TIM5) Figure 131. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MSv37302V1 Figure 132. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 490: Figure 133. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 to TIM5) RM0402 Figure 133. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 491: Figure 134. Counter Timing Diagram, Internal Clock Divided By 1
RM0402 General-purpose timers (TIM2 to TIM5) Figure 134. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timerclock = CK_CNT Counter register 04 03 02 01 00 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MSv37305V1 Figure 135.
Page 492: Figure 137. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0402 Figure 137. Counter timing diagram, internal clock divided by N CK_INT Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS37340V1 Figure 138. Counter timing diagram, Update event CK_INT CNT_EN Timerclock = CK_CNT Counter register...
Page 493: Figure 139. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0402 General-purpose timers (TIM2 to TIM5) In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.
Page 494: Figure 140. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0402 Figure 140. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timerclock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS37343V1 Figure 141.
Page 495: Figure 143. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0402 General-purpose timers (TIM2 to TIM5) Figure 143. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timerclock = CK_CNT Counter register 05 04 03 02 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 496: Clock Selection
General-purpose timers (TIM2 to TIM5) RM0402 17.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.
Page 497: Figure 146. Ti2 External Clock Connection Example
RM0402 General-purpose timers (TIM2 to TIM5) Figure 146. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode...
Page 498: Figure 147. Control Circuit In External Clock Mode 1
General-purpose timers (TIM2 to TIM5) RM0402 Figure 147. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 499: Capture/Compare Channels
RM0402 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 149. Control circuit in external clock mode 2 CK_INT CNT_EN ETRP...
Page 500: Figure 150. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2 to TIM5) RM0402 Figure 150. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P/CC1NP ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising...
Page 501: Input Capture Mode
RM0402 General-purpose timers (TIM2 to TIM5) Figure 152. Output stage of capture/compare channel (channel 1) OCREF_CLR OCREF_CLR_INT ETRF To the master mode controller Output OCCS Enable Circuit TIMx_SMCR CC1P CNT > CCR1 Output mode oc1ref TIMx_CCER CNT = CCR1 controller CC1E TIMx_CCER OC1M[2:0]...
Page 502: Pwm Input Mode
General-purpose timers (TIM2 to TIM5) RM0402 new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
Page 503: Forced Output Mode
RM0402 General-purpose timers (TIM2 to TIM5) For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): •...
Page 504: Output Compare Mode
General-purpose timers (TIM2 to TIM5) RM0402 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 17.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 505: Pwm Mode
RM0402 General-purpose timers (TIM2 to TIM5) Figure 154. Output compare mode, toggle on OC1 Write B201h in the CC1R register TIMx_CNT 0039 003A 003B B200 B201 TIMx_CCR1 003A B201 OC1REF = OC1 Match detected on CCR1 Interrupt generated if enabled MS37363V1 17.3.9 PWM mode...
Page 506: Figure 155. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0402 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 487. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low.
Page 507: Figure 156. Center-Aligned Pwm Waveforms (Arr=8)
RM0402 General-purpose timers (TIM2 to TIM5) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 492. Figure 156 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, •...
Page 508: One-Pulse Mode
General-purpose timers (TIM2 to TIM5) RM0402 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 509: Clearing The Ocxref Signal On An External Event
RM0402 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 510: Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0402 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 511: Table 99. Counting Direction Versus Encoder Signals
RM0402 General-purpose timers (TIM2 to TIM5) In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.
Page 512: Figure 159. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0402 Figure 159. Example of counter operation in encoder interface mode forward jitter backward jitter forward Counter down MS33107V1 Figure 160 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 160.
Page 513: Timer Input Xor Function
RM0402 General-purpose timers (TIM2 to TIM5) 17.3.13 Timer input XOR function The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 514: Figure 162. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0402 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 515: Figure 163. Control Circuit In Trigger Mode
RM0402 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 163. Control circuit in trigger mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 35 36 37 38...
Page 516: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0402 Figure 164. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register MS33110V1 17.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 517: Figure 166. Gating Timer 2 With Oc1Ref Of Timer 1
RM0402 General-purpose timers (TIM2 to TIM5) For example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to Figure 165. To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV.
Page 518: Figure 167. Gating Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0402 in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0.
Page 519: Figure 168. Triggering Timer 2 With Update Of Timer 1
RM0402 General-purpose timers (TIM2 to TIM5) counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3). CK_CNT CK_INT • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register).
Page 520: Figure 169. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0402 Figure 169. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2-write CNT TIMER2-TIF Write TIF = 0 MS37391V1 Using one timer as prescaler for another timer For example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to Figure 165 for connections.
Page 521: Debug Mode
RM0402 General-purpose timers (TIM2 to TIM5) counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): • Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).
Page 522: Tim2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0402 17.4 TIM2 to TIM5 registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits).
Page 523 RM0402 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 524: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Page 525: Timx Slave Mode Control Register (Timx_Smcr)
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 526: Table 100. Timx Internal Trigger Connections
General-purpose timers (TIM2 to TIM5) RM0402 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 527: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 528: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0402 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 17.4.5...
Page 529 RM0402 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 530: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 531: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 532 General-purpose timers (TIM2 to TIM5) RM0402 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 533 RM0402 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 534: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 535: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0402 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 536: Table 101. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 to TIM5) RM0402 Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity.
Page 537: Timx Counter (Timx_Cnt)
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 538: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 539: Timx Capture/Compare Register 3 (Timx_Ccr3)
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
Page 540: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 541: Tim2 Option Register (Tim2_Or)
RM0402 General-purpose timers (TIM2 to TIM5) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 542: Tim5 Option Register (Tim5_Or)
General-purpose timers (TIM2 to TIM5) RM0402 17.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP Res. Res. Res. Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software.
Page 543: Timx Register Map
RM0402 General-purpose timers (TIM2 to TIM5) 17.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 102. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS...
Page 544 General-purpose timers (TIM2 to TIM5) RM0402 Table 102. TIM2 to TIM5 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved CCR1[31:16]...
Page 545: General-Purpose Timers (Tim9 To Tim14)
RM0402 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) 18.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM).
Page 546: Tim10/Tim11 And Tim13/Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0402 Figure 171. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I...
Page 547: Figure 172. General-Purpose Timer Block Diagram (Tim10/11/13/14)
RM0402 General-purpose timers (TIM9 to TIM14) Figure 172. General-purpose timer block diagram (TIM10/11/13/14) Internal clock (CK_INT) Enable Trigger counter Controller Autoreload register Stop, Clear CK_PSC CK_CNT prescaler counter CC1I CC1I TI1FP1 output Input filter & IC1PS OC1REF Prescaler Capture/Compare 1 register TIMx_CH1 TIMx_CH1 edge detector...
Page 548: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0402 18.3 TIM9 to TIM14 functional description 18.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 549: Figure 173. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0402 General-purpose timers (TIM9 to TIM14) Figure 173. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 174.
Page 550: Counter Modes
General-purpose timers (TIM9 to TIM14) RM0402 18.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event.
Page 551: Figure 176. Counter Timing Diagram, Internal Clock Divided By 2
RM0402 General-purpose timers (TIM9 to TIM14) Figure 176. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V3 Figure 177.
Page 552: Figure 179. Counter Timing Diagram, Update Event When Arpe=0
General-purpose timers (TIM9 to TIM14) RM0402 Figure 179. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 180.
Page 553: Clock Selection
RM0402 General-purpose timers (TIM9 to TIM14) 18.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer.
Page 554: Figure 182. Ti2 External Clock Connection Example
General-purpose timers (TIM9 to TIM14) RM0402 Figure 182. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F ITRx TI1_ED CK_PSC TRGI External clock TI1FP1 mode 1 TI2F_Rising Edge TI2FP2 Filter detector TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0] CC2P TIMx_CCER TIMx_CCMR1 SMS[2:0]...
Page 555: Capture/Compare Channels
RM0402 General-purpose timers (TIM9 to TIM14) 18.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 184 Figure 186 give an overview of one capture/compare channel.
Page 556: Input Capture Mode
General-purpose timers (TIM9 to TIM14) RM0402 Figure 185. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H Read CCR1H write_in_progress read_in_progress write CCR1L Capture/compare preload register Read CCR1L Output CC1S[1] compare_transfer mode capture_transfer CC1S[0] Input CC1S[1] OC1PE mode OC1PE Capture /compare shadow register CC1S[0]...
Page 557: Pwm Input Mode (Only For Tim9/12)
RM0402 General-purpose timers (TIM9 to TIM14) cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 558: Forced Output Mode
General-purpose timers (TIM9 to TIM14) RM0402 Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 559: Output Compare Mode
RM0402 General-purpose timers (TIM9 to TIM14) 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 560: Pwm Mode
General-purpose timers (TIM9 to TIM14) RM0402 Figure 188. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A 003B B200 B201 TIM1_CCR1 003A B201 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V2 18.3.9 PWM mode Pulse Width Modulation mode allows to generate a signal with a frequency determined by...
Page 561: One-Pulse Mode
RM0402 General-purpose timers (TIM9 to TIM14) Figure 189. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF ‘1’ CCRx>8 CCxIF ‘0’ OCXREF CCRx=0 CCxIF MS31093V1 18.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 562: Figure 190. Example Of One Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0402 Figure 190. Example of one pulse mode. OC1REF TIM1_ARR TIM1_CCR1 DELAY PULSE MS31099V1 For example one may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin.
Page 563: Tim9/12 External Trigger Synchronization
RM0402 General-purpose timers (TIM9 to TIM14) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle.
Page 564: Figure 191. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0402 Figure 191. Control circuit in reset mode Counter clock = ck_cnt = ck_psc Counter register 32 33 34 35 36 01 02 03 00 01 02 03 MS31401V2 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1.
Page 565: Figure 192. Control Circuit In Gated Mode
RM0402 General-purpose timers (TIM9 to TIM14) Figure 192. Control circuit in gated mode cnt_en Counter clock = ck_cnt = ck_psc Counter register 32 33 35 36 Write TIF=0 MS31402V1 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2.
Page 566: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0402 18.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 17.3.15: Timer synchronization for details. 18.3.13 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
Page 567 RM0402 General-purpose timers (TIM9 to TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 568: Tim9/12 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM9 to TIM14) RM0402 18.4.2 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 569: Tim9/12 Interrupt Enable Register (Timx_Dier)
RM0402 General-purpose timers (TIM9 to TIM14) Table 103. TIMx internal trigger connections Slave TIM ITR0 (TS = ‘000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ‘011’) TIM9 TIM2 TIM3 TIM10_OC TIM11_OC TIM12 TIM4 TIM5 TIM13_OC TIM14_OC 18.4.3 TIM9/12 Interrupt enable register (TIMx_DIER) Address offset: 0x0C...
Page 570: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0402 18.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. Res. Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag...
Page 571 RM0402 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 572: Tim9/12 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0402 18.4.5 TIM9/12 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 573 RM0402 General-purpose timers (TIM9 to TIM14) Output compare mode Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input.
Page 574 General-purpose timers (TIM9 to TIM14) RM0402 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 575 RM0402 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 576: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0402 18.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value.
Page 577: Tim9/12 Counter (Timx_Cnt)
RM0402 General-purpose timers (TIM9 to TIM14) Table 104. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 578: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0402 18.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 579: Tim9/12 Register Map
RM0402 General-purpose timers (TIM9 to TIM14) 18.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: Table 105. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reset value TIMx_DIER 0x0C...
Page 580 General-purpose timers (TIM9 to TIM14) RM0402 Table 105. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Reserved 0x4C Refer to Section 2.2 on page 49 for the register boundary addresses. 580/1163 RM0402 Rev 6...
Page 581: Tim10/11/13/14 Registers
RM0402 General-purpose timers (TIM9 to TIM14) 18.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 18.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 582: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0402 18.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled...
Page 583: Tim10/11/13/14 Event Generation Register (Timx_Egr)
RM0402 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 584: Tim10/11/13/14 Capture/Compare Mode Register 1
General-purpose timers (TIM9 to TIM14) RM0402 18.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 585 RM0402 General-purpose timers (TIM9 to TIM14) Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 586 General-purpose timers (TIM9 to TIM14) RM0402 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 587: Tim10/11/13/14 Capture/Compare Enable Register
RM0402 General-purpose timers (TIM9 to TIM14) 18.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity.
Page 588: Tim10/11/13/14 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0402 18.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 589: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
RM0402 General-purpose timers (TIM9 to TIM14) 18.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 590: Tim10/11/13/14 Register Map
General-purpose timers (TIM9 to TIM14) RM0402 18.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 107. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR 0x08 Reset value TIMx_DIER...
Page 591 RM0402 General-purpose timers (TIM9 to TIM14) Table 107. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value 0x38 to Reserved 0x4C TIMx_OR 0x50 Reset value Refer to Section 2.2.2 on page 50 for the register boundary addresses. RM0402 Rev 6 591/1163...
Page 592: Basic Timers (Tim6/7)
Basic timers (TIM6/7) RM0402 Basic timers (TIM6/7) 19.1 Introduction The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. 19.2 TIM6/7 main features Basic timer (TIM6/TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 •...
Page 593: Tim6/7 Functional Description
RM0402 Basic timers (TIM6/7) 19.3 TIM6/7 functional description 19.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 594: Figure 195. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6/7) RM0402 Figure 195. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 196.
Page 595: Counting Mode
RM0402 Basic timers (TIM6/7) 19.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 596: Figure 198. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6/7) RM0402 Figure 198. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0035 0036 0000 0001 0002 0003 0034 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 199. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 597: Figure 200. Counter Timing Diagram, Internal Clock Divided By N
RM0402 Basic timers (TIM6/7) Figure 200. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 201. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 598: Clock Source
Basic timers (TIM6/7) RM0402 Figure 202. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 599: Debug Mode
RM0402 Basic timers (TIM6/7) Figure 203. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 19.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the...
Page 600: Tim6/7 Registers
Basic timers (TIM6/7) RM0402 19.4 TIM6/7 registers Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
Page 601: Tim6/7 Control Register 2 (Timx_Cr2)
RM0402 Basic timers (TIM6/7) 19.4.2 TIM6/7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 602: Tim6/7 Status Register (Timx_Sr)
Basic timers (TIM6/7) RM0402 19.4.4 TIM6/7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 603: Tim6/7 Prescaler (Timx_Psc)
RM0402 Basic timers (TIM6/7) 19.4.7 TIM6/7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
Page 604: Tim6/7 Register Map
Basic timers (TIM6/7) RM0402 19.4.9 TIM6/7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 108. TIM6/7 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Res.
Page 605: Independent Watchdog (Iwdg)
RM0402 Independent watchdog (IWDG) Independent watchdog (IWDG) 20.1 IWDG introduction The devices feature two embedded watchdog peripherals that offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.
Page 606: Debug Mode
Independent watchdog (IWDG) RM0402 A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. 20.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module.
Page 607: Iwdg Registers
RM0402 Independent watchdog (IWDG) 20.4 IWDG registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 20.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 608: Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0402 20.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 609: Reload Register (Iwdg_Rlr)
RM0402 Independent watchdog (IWDG) 20.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 610: Iwdg Register Map
Independent watchdog (IWDG) RM0402 Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete)
Page 611: Window Watchdog (Wwdg)
RM0402 Window watchdog (WWDG) Window watchdog (WWDG) 21.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
Page 612: Figure 205. Watchdog Block Diagram
Window watchdog (WWDG) RM0402 Figure 205. Watchdog block diagram RESET Watchdog configuration register (WWDG_CFR) comparator =1 when T6:0 > W6:0 Write WWDG_CR Watchdog control register (WWDG_CR) WDGA T6 7-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler /4096 (WDGTB) MSv37226V2 The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 613: How To Program The Watchdog Timeout
RM0402 Window watchdog (WWDG) In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions.
Page 614: Debug Mode
Window watchdog (WWDG) RM0402 As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 1 24000 4096 21.85 ms Refer to the datasheets for the minimum and maximum values of the t WWDG.
Page 615: Wwdg Registers
RM0402 Window watchdog (WWDG) 21.6 WWDG registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 21.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res.
Page 616: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0402 21.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40.
Page 617: Wwdg Register Map
RM0402 Window watchdog (WWDG) 21.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 111. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value Refer to...
Page 618: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0402 Real-time clock (RTC) 22.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to manage low power modes.
Page 619 RM0402 Real-time clock (RTC) – 0.95 ppm accuracy, obtained in a calibration window of several seconds • Timestamp function for event saving (1 event) • Tamper detection: – 2 tamper events with configurable filter and internal pull-up. • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.
Page 620: Rtc Functional Description
Real-time clock (RTC) RM0402 22.3 RTC functional description 22.3.1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 6: Reset and clock control (RCC) for STM32F412xx.
Page 621: Programmable Alarms
RM0402 Real-time clock (RTC) Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 22.6.4). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to two RTCCLK periods.
Page 622: Rtc Initialization And Configuration
Real-time clock (RTC) RM0402 complete (see Programming the wakeup timer), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).
Page 623 RM0402 Real-time clock (RTC) factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
Page 624: Reading The Calendar
Real-time clock (RTC) RM0402 22.3.6 Reading the calendar BYPSHAD control bit is cleared in the RTC_CR register When To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (f ) must be equal to or greater than seven times the f PCLK1 RTCCLK clock frequency.
Page 625: Resetting The Rtc
RM0402 Real-time clock (RTC) 22.3.7 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are resetted to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR or RTC_CALR), the RTC shift register (RTC_SHIFTR),...
Page 626: Rtc Reference Clock Detection
Real-time clock (RTC) RM0402 22.3.9 RTC reference clock detection The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).
Page 627: Rtc Smooth Digital Calibration
RM0402 Real-time clock (RTC) When positive calibration is enabled (DCS = ‘0’), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher. When negative calibration is enabled (DCS = ‘1’), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xDC minutes.
Page 628 Real-time clock (RTC) RM0402 The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle.
Page 629: Timestamp Function
RM0402 Real-time clock (RTC) Verifying the RTC calibration RTC precision is performed by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
Page 630: Tamper Detection
Real-time clock (RTC) RM0402 If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.
Page 631: Calibration Clock Output
RM0402 Real-time clock (RTC) Edge detection on tamper inputs If the TAMPFLT bits are “00”, the TAMPER pins generate tamper detection events (RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMPER inputs are deactivated when edge detection is selected.
Page 632: Alarm Output
Real-time clock (RTC) RM0402 The RTC_CALIB output is not impacted by the calibration value programmed in RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. If COSEL is set and “PREDIV_S+1”...
Page 633: Rtc Interrupts
RM0402 Real-time clock (RTC) 22.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. To enable the RTC Alarm interrupt, the following sequence is required: Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.
Page 634: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected.
Page 635: Rtc Date Register (Rtc_Dr)
RM0402 Real-time clock (RTC) 22.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration Reading the calendar. Address offset: 0x04 Backup domain reset value: 0x0000_2101 System reset: 0x0000 2101 when BYPSHAD = 0.
Page 636: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0402 22.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE DCE FMT BYPSHAD REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value.
Page 637 RM0402 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
Page 638: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0402 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection...
Page 639 RM0402 Real-time clock (RTC) Bit 13 TAMP1F: Tamper detection flag This flag is set by hardware when a tamper detection event is detected. It is cleared by software writing 0. Bit 12 TSOVF: Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. This flag is cleared by software by writing 0.
Page 640: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0402 Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR.
Page 641: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0402 Real-time clock (RTC) Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) Note:...
Page 642 Real-time clock (RTC) RM0402 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DC[4:0] Bits 31:8 Reserved, must be kept at reset value Bit 7 DCS: Digital calibration sign 0: Positive calibration: calendar update frequency is increased 1: Negative calibration: calendar update frequency is decreased...
Page 643: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.
Page 644: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.
Page 645: Rtc Write Protection Register (Rtc_Wpr)
RM0402 Real-time clock (RTC) 22.6.10 RTC write protection register (RTC_WPR) Address offset: 0x24 Backup domain reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 646: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0402 22.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect...
Page 647: Rtc Time Stamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR.
Page 648: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0402 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note:...
Page 649: Rtc Tamper And Alternate Function Configuration Register
RM0402 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
Page 650 Real-time clock (RTC) RM0402 Bits 31:19 Reserved, must be kept at reset value. Always read as 0. Bit 18 ALARMOUTTYPE: RTC_ALARM output type 0: RTC_ALARM is an open-drain output 1: RTC_ALARM is a push-pull output Bit 17 TSINSEL: TIMESTAMP mapping 0: RTC_AF1 used as TIMESTAMP 1: Reserved Bit 16 TAMP1INSEL: TAMPER1 mapping...
Page 651: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
RM0402 Real-time clock (RTC) Bits 6:3 Reserved. Always read as 0. Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled Bit 1 TAMP1TRG: Active level for tamper 1 if TAMPFLT != 00: 0: TAMPER1 staying low triggers a tamper detection event. 1: TAMPER1 staying high triggers a tamper detection event.
Page 652: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0402 Bits 23:15 Reserved, must be kept at reset value Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.
Page 653: Rtc Backup Registers (Rtc_Bkpxr)
This register is reset on a tamper detection event, as long as TAMPxF=1. 22.6.21 RTC register map Table 114. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0]...
Page 654 Real-time clock (RTC) RM0402 Table 114. RTC register map and reset values (continued) Offset Register RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x1C Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] [1:0] 0x20 Reset value RTC_WPR...
Page 655 RM0402 Real-time clock (RTC) Table 114. RTC register map and reset values (continued) Offset Register RTC_BKP0R BKP[31:0] Reset value 0x50 to 0x9C BKP[31:0] RTC_BKP19R Reset value Refer to Section 2.2 on page 49 for the register boundary addresses. Caution: Table 114, the reset value is the value after a backup domain reset.
Page 656: Fast-Mode Plus Inter-Integrated Circuit (Fmpi2C) Interface
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
Page 657: Fmpi2C Implementation
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The following additional features are also available depending on the product implementation (see Section 23.3: FMPI2C implementation): • SMBus specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control –...
Page 658: Fmpi2C Block Diagram
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.4.1 FMPI2C block diagram The block diagram of the FMPI2C interface is shown in Figure 208. Figure 208. FMPI2C block diagram I2CCLK I2c_ker_ck Data control Digital Analog Shift register noise noise GPIO I2C_SDA filter filter logic...
Page 659: Fmpi2C Pins And Internal Signals
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.4.2 FMPI2C pins and internal signals Table 116. FMPI2C input/output pins Pin name Signal type Description I2C_SDA Bidirectional I2C data I2C_SCL Bidirectional I2C clock I2C_SMBA Bidirectional SMBus alert Table 117. FMPI2C internal input/output signals Internal signal name Signal type Description...
Page 660: Mode Selection
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.4.4 Mode selection The interface can operate in one of the four following modes: • Slave transmitter • Slave receiver • Master transmitter • Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master when it generates a START condition, and from master to slave if an arbitration loss or a STOP generation occurs, allowing multimaster capability.
Page 661: Table 118. Comparison Of Analog Vs. Digital Filters
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When the FMPI2C is disabled (PE=0), the I C performs a software reset. Refer to Section 23.4.6: Software reset for more details. Noise filters Before enabling the FMPI2C peripheral by setting the PE bit in FMPI2C_CR1 register, the user must configure the noise filters, if needed.
Page 662: Figure 210. Setup And Hold Timings
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 FMPI2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 210.
Page 663: Table 119. I2C-Smbus Specification Data Setup And Hold Times
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
Page 664 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t...
Page 665: Software Reset
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 211. FMPI2C initialization flowchart Initial settings Clear PE bit in FMPI2C_CR1 Configure ANFOFF and DNF[3:0] in FMPI2C_CR1 Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in FMPI2C_TIMINGR Configure NOSTRETCH in FMPI2C_CR1 Set PE bit in FMPI2C_CR1 MSv35962V1 23.4.6 Software reset...
Page 666: Data Transfer
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.4.7 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0).
Page 667: Figure 213. Data Transmission
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Transmission If the FMPI2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in FMPI2C_TXDR, SCL line is stretched low until FMPI2C_TXDR is written.
Page 668: Fmpi2C Slave Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the FMPI2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field is transferred.
Page 669 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in the FMPI2C_CR1 register.
Page 670: Figure 214. Slave Initialization Flowchart
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Slave byte control mode In order to allow byte ACK control in slave reception mode, The Slave byte control mode must be enabled by setting the SBC bit in the FMPI2C_CR1 register. This is required to be compliant with SMBus standards.
Page 671 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave transmitter A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register. The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte to be transmitted.
Page 672: Figure 215. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 215. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH= 0 Slave transmission Slave initialization FMPI2C_ISR.ADDR stretched Read ADDCODE and DIR in FMPI2C_ISR Optional: Set FMPI2C_ISR.TXE = 1 Set FMPI2C_ICR.ADDRCF FMPI2C_ISR.TXIS Write FMPI2C_TXDR.TXDATA MSv35964V1 672/1163 RM0402 Rev 6...
Page 673: Figure 216. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 216. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH= 1 Slave transmission Slave initialization FMPI2C_ISR.STOPF FMPI2C_ISR.TXIS Write FMPI2C_TXDR.TXDATA Optional: Set FMPI2C_ISR.TXE = 1 and FMPI2C_ISR.TXIS=1 Set FMPI2C_ICR.STOPCF MSv35965V1 RM0402 Rev 6 673/1163...
Page 674: Figure 217. Transfer Bus Diagrams For Fmpi2C Slave Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 217. Transfer bus diagrams for FMPI2C slave transmitter legend: Example FMPI2C slave transmitter 3 bytes with 1st data flushed NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch data3 Address data1 data2 EV4 EV5 EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF...
Page 675: Figure 218. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave receiver RXNE is set in FMPI2C_ISR when the FMPI2C_RXDR is full, and generates an interrupt if RXIE is set in FMPI2C_CR1. RXNE is cleared when FMPI2C_RXDR is read. When a STOP is received and STOPIE is set in FMPI2C_CR1, STOPF is set in FMPI2C_ISR and an interrupt is generated.
Page 676: Figure 219. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 219. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Slave reception Slave initialization FMPI2C_ISR.STOPF FMPI2C_ISR.RXNE Set FMPI2C_ICR.STOPCF Read FMPI2C_RXDR.RXDATA MSv35967V1 Figure 220. Transfer bus diagrams for FMPI2C slave receiver legend: Example FMPI2C slave receiver 3 bytes, NOSTRETCH=0: transmission ADDR RXNE...
Page 677: Fmpi2C Master Mode
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.4.9 FMPI2C master mode FMPI2C master initialization Before enabling the peripheral, the FMPI2C master clock must be configured by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 678: Figure 221. Master Clock Generation
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 221. Master clock generation SCL master clock generation SCL high level detected SCLH counter starts SCLH SYNC2 SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL master clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 679: Table 121. I2C-Smbus Specification Clock Timings
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 121. I C-SMBus specification clock timings Standard- Fast-mode Fast-mode SMBus mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START condition 0.26 µs HD:STA Set-up time for a repeated START 0.26 µs SU:STA...
Page 680: Figure 222. Master Initialization Flowchart
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 master re-launches automatically the slave address transmission until ACK is received. In this case ADDRCF must be set if a NACK is received from the slave, in order to stop sending the slave address. If the FMPI2C is addressed as a slave (ADDR=1) while the START bit is set, the FMPI2C switches to slave mode and the START bit is cleared, when the ADDRCF bit is set.
Page 681: Figure 224. 10-Bit Address Read Access With Head10R=1
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read.
Page 682: Figure 225. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N≤255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 225. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes Master transmission Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set FMPI2C_CR2.START FMPI2C_ISR.TXIS FMPI2C_ISR.NACKF = 1? = 1?
Page 683: Figure 226. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N>255 Bytes
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 226. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes Master transmission Master initialization NBYTES = 0xFF; N=N-255 RELOAD = 1 Configure slave address Set FMPI2C_CR2.START FMPI2C_ISR.TXIS FMPI2C_ISR.NACKF = 1? = 1? Write FMPI2C_TXDR NBYTES transmitted...
Page 684: Figure 227. Transfer Bus Diagrams For Fmpi2C Master Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 227. Transfer bus diagrams for FMPI2C master transmitter Example FMPI2C master transmitter 2 bytes, automatic end mode (STOP) legend: TXIS TXIS transmission reception Address data1 data2 SCL stretch INIT EV1 EV2 NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: TXIS ISR: wr data1 EV2: TXIS ISR: wr data2...
Page 685 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1 register.
Page 686: Figure 228. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N≤255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 228. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes Master reception Master initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure slave address Set FMPI2C_CR2.START FMPI2C_ISR.RXNE Read FMPI2C_RXDR NBYTES received?
Page 687: Figure 229. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N >255 Bytes
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 229. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes Master reception Master initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure slave address Set FMPI2C_CR2.START FMPI2C_ISR.RXNE = 1? Read FMPI2C_RXDR NBYTES received? FMPI2C_ISR.TC...
Page 688: Figure 230. Transfer Bus Diagrams For Fmpi2C Master Receiver
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 230. Transfer bus diagrams for FMPI2C master receiver Example FMPI2C master receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission Address data1 data2 reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 Example FMPI2C master receiver 2 bytes,software end mode (RESTART)
Page 689: Fmpi2C_Timingr Register Configuration Examples
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.4.10 FMPI2C_TIMINGR register configuration examples The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, the STM32CubeMX tool (I2C Configuration window) must be used. Table 122.
Page 690: Smbus Specific Features
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 2. t minimum value is 4 x t = 250 ns. Example with t = 1000 ns. SYNC1 + SYNC2 I2CCLK SYNC1 + SYNC2 minimum value is 4 x t = 250 ns. Example with t = 750 ns.
Page 691 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Received command and data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in FMPI2C_CR1 register.
Page 692: Table 124. Smbus Timeout Specifications
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification. Table 124. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT Cumulative clock low extend time (master device)
Page 693: Smbus Initialization
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 119: I2C-SMBus specification data IDLE HIGH setup and hold...
Page 694: Table 125. Smbus With Pec Configuration
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Table 125. SMBus with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the FMPI2C_TIMEOUTR register.
Page 695: Smbus: Fmpi2C_Timeoutr Register Configuration Examples
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Refer to Table 128: Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max t = 50 µs) IDLE Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 23.4.13 FMPI2C_TIMEOUTR register configuration examples...
Page 696: Figure 232. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 FMPI2C_PECR register is automatically transmitted if the master requests an extra byte after the NBYTES-1 data transfer. Caution: The PECBYTE bit has no effect when the RELOAD bit is set. Figure 232. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC SMBus slave transmission Slave initialization...
Page 697: Figure 233. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 233. Transfer bus diagrams for SMBus slave transmitter (SBC=1) legend: Example SMBus slave transmitter 2 bytes + PEC, transmission ADDR TXIS TXIS reception SCL stretch Address data1 data2 NBYTES EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF EV2: TXIS ISR: wr data1 EV3: TXIS ISR: wr data2 MS19869V2...
Page 698: Figure 234. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 234. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC SMBus slave reception Slave initialization FMPI2C_ISR.ADDR = 1? Read ADDCODE and DIR in FMPI2C_ISR stretched FMPI2C_CR2.NBYTES = 1, RELOAD =1 PECBYTE=1 Set FMPI2C_ICR.ADDRCF FMPI2C_ISR.RXNE =1?
Page 699: Figure 235. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 235. Bus transfer diagrams for SMBus slave receiver (SBC=1) legend: Example SMBus slave receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception Address data1 data2 SCL stretch NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 700: Figure 236. Bus Transfer Diagrams For Smbus Master Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the FMPI2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low.
Page 701 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface SMBus master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
Page 702: Error Conditions
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Figure 237. Bus transfer diagrams for SMBus master receiver Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1...
Page 703 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When a bus error is detected, the BERR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register. Arbitration lost (ARLO) An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge.
Page 704: Dma Requests
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Timeout Error (TIMEOUT) This section is relevant only when the SMBus feature is supported. Refer to Section 23.3: FMPI2C implementation. A timeout error occurs for any of these conditions: • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout.
Page 705: Debug Mode
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface initialized before setting the START bit. The end of transfer is managed with the NBYTES counter. Refer to Master transmitter on page 681. • In slave mode: – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
Page 706: Fmpi2C Interrupts
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.6 FMPI2C interrupts The table below gives the list of FMPI2C interrupt requests. Table 130. FMPI2C Interrupt requests Exit the Exit the Exit the Interrupt Interrupt Event Enable Interrupt clear Sleep Stop Standby acronym event flag...
Page 707: Fmpi2C Registers
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7 FMPI2C registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 23.7.1 FMPI2C control register 1 (FMPI2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is...
Page 708 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Bit 19 GCEN: General call enable 0: General call disabled. Address 0b00000000 is NACKed. 1: General call enabled. Address 0b00000000 is ACKed. Bit 18 Reserved, must be kept at reset value. Bit 17 NOSTRETCH: Clock stretching disable This bit is used to disable clock stretching in slave mode.
Page 709: Fmpi2C Control Register 2 (Fmpi2C_Cr2)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 6 TCIE: Transfer Complete interrupt enable 0: Transfer Complete interrupt disabled 1: Transfer Complete interrupt enabled Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR) Bit 5 STOPIE: Stop detection Interrupt enable 0: Stop detection (STOPF) interrupt disabled 1: Stop detection (STOPF) interrupt enabled Bit 4 NACKIE: Not acknowledge received Interrupt enable...
Page 710 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Bits 31:27 Reserved, must be kept at reset value. Bit 26 PECBYTE: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0.
Page 711 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 13 START: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing ‘1’...
Page 712: Fmpi2C Own Address 1 Register (Fmpi2C_Oar1)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.7.3 FMPI2C own address 1 register (FMPI2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 713: Fmpi2C Own Address 2 Register (Fmpi2C_Oar2)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.4 FMPI2C own address 2 register (FMPI2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 714: Fmpi2C Timing Register (Fmpi2C_Timingr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.7.5 FMPI2C timing register (FMPI2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale FMPI2CCLK in order to generate the clock period t used PRESC for data setup and hold counters (refer to...
Page 715: Fmpi2C Timeout Register (Fmpi2C_Timeoutr)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.6 FMPI2C timeout register (FMPI2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 716: Fmpi2C Interrupt And Status Register (Fmpi2C_Isr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.7.7 FMPI2C interrupt and status register (FMPI2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS...
Page 717 RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
Page 718: Fmpi2C Interrupt Clear Register (Fmpi2C_Icr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read. Note: This bit is cleared by hardware when PE=0.
Page 719: Fmpi2C Pec Register (Fmpi2C_Pecr)
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register. Bit 9 ARLOCF: Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.
Page 720: Fmpi2C Receive Data Register (Fmpi2C_Rxdr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 23.7.10 FMPI2C receive data register (FMPI2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 721: Fmpi2C Register Map
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 23.7.12 FMPI2C register map The table below provides the FMPI2C register map and reset values. Table 131. FMPI2C register map and reset values Register Offset name FMPI2C_CR1 DNF[3:0] Reset value FMPI2C_CR2 NBYTES[7:0] SADD[9:0] Reset value FMPI2C_OAR1 OA1[9:0]...
Page 722 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402 Table 131. FMPI2C register map and reset values (continued) Register Offset name FMPI2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2 on page 49 for the register boundary addresses. 722/1163 RM0402 Rev 6...
Page 723: Inter-Integrated Circuit
RM0402 Inter-integrated circuit (I C) interface Inter-integrated circuit (I C) interface 24.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.
Page 724: I 2 C Main Features
Inter-integrated circuit (I C) interface RM0402 24.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –...
Page 725: C Functional Description
RM0402 Inter-integrated circuit (I C) interface Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I C interface implementation. 24.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel...
Page 726: I2C Slave Mode
Inter-integrated circuit (I C) interface RM0402 The block diagram of the I C interface is shown in Figure 239. Figure 239. I C block diagram Data register Data Noise Data shift register control filter PEC calculation Comparator Own address register Dual address register Clock Noise...
Page 727 RM0402 Inter-integrated circuit (I C) interface Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address. Header or address not matched: the interface ignores it and waits for another Start condition.
Page 728: Figure 240. Transfer Sequence Diagram For Slave Transmitter
Inter-integrated circuit (I C) interface RM0402 Figure 240. Transfer sequence diagram for slave transmitter 7-bit slave transmitter S A ddress Data1 Data2 DataN ..EV1 EV3-1 EV3-2 10-bit slave transmitter Header Address Header Data1 DataN ..EV1 EV3_1 EV3-2 Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge , EVx= Event (with interrupt if ITEVFEN=1) AV1: ADDR=1, cleared by reading SR1 followed by reading SR2...
Page 729: I2C Master Mode
RM0402 Inter-integrated circuit (I C) interface Figure 241. Transfer sequence diagram for slave receiver 7-bit slave receiver DataN Address Data1 Data2 ..10-bit slav e receiver DataN Address Data1 Header ..Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV1: ADDR=1, cleared by reading SR1 followed by reading SR2 EV2: RxNE=1 cleared by reading DR register.
Page 730 Inter-integrated circuit (I C) interface RM0402 SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 731 RM0402 Inter-integrated circuit (I C) interface The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 732: Figure 242. Transfer Sequence Diagram For Master Transmitter
Inter-integrated circuit (I C) interface RM0402 Figure 242. Transfer sequence diagram for master transmitter 7-bit master transmitter Address Data1 Data2 DataN ..EV8_2 EV6 EV8_1 10-bit master transmitter DataN Header Address Data1 ..EV8_1 EV8_2 Legend: S = Start, SR = Repeated start, P = stop, A = Acknowledge EVx = Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register with address.
Page 733 RM0402 Inter-integrated circuit (I C) interface Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 734: Figure 243. Transfer Sequence Diagram For Master Receiver
Inter-integrated circuit (I C) interface RM0402 Figure 243. Transfer sequence diagram for master receiver 7-bit master receiver Address Data1 Data2 DataN ..EV7_1 10-bit master receiver Header Address Data1 Data2 DataN Header ..EV7_1 Leg end : S= Start, S = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register.
Page 735: Error Conditions
RM0402 Inter-integrated circuit (I C) interface For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
Page 736: Programmable Noise Filter
Inter-integrated circuit (I C) interface RM0402 Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface.
Page 737: Sda/Scl Line Control
RM0402 Inter-integrated circuit (I C) interface Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation. 24.3.6 SDA/SCL line control •...
Page 738: Table 133. Smbus Vs. I2C
Inter-integrated circuit (I C) interface RM0402 Table 133. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed Logic levels are V dependent Different address types (reserved, dynamic etc.)
Page 739 RM0402 Inter-integrated circuit (I C) interface SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. SMBA is used in conjunction with the SMBus General Call Address.
Page 740: Dma Requests
Inter-integrated circuit (I C) interface RM0402 24.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
Page 741: Packet Error Checking
RM0402 Inter-integrated circuit (I C) interface Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data are loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 742: I 2 C Interrupts
Inter-integrated circuit (I C) interface RM0402 be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
Page 743: Figure 244. I2C Interrupt Mapping Diagram
RM0402 Inter-integrated circuit (I C) interface Figure 244. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT RM0402 Rev 6 743/1163...
Page 744: I 2 C Debug Mode
Inter-integrated circuit (I C) interface RM0402 24.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 30.16.2: Debug support for timers, watchdog, bxCAN and I 24.6...
Page 745 RM0402 Inter-integrated circuit (I C) interface Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 746: I 2 C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I C) interface RM0402 Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
Page 747 RM0402 Inter-integrated circuit (I C) interface ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 –...
Page 748: I 2 C Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I C) interface RM0402 24.6.3 C own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. ADD[9:8] ADD[7:1] ADD0 MODE Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 749: C Data Register (I2C_Dr)
RM0402 Inter-integrated circuit (I C) interface 24.6.5 C data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. DR[7:0] Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus.
Page 750 Inter-integrated circuit (I C) interface RM0402 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 751 RM0402 Inter-integrated circuit (I C) interface Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 752 Inter-integrated circuit (I C) interface RM0402 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 753: I 2 C Status Register 2 (I2C_Sr2)
RM0402 Inter-integrated circuit (I C) interface 24.6.7 C status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 754: I 2 C Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I C) interface RM0402 Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 755: I 2 C Trise Register (I2C_Trise)
RM0402 Inter-integrated circuit (I C) interface Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Note: When the PCLK frequency is a multiple of 10 MHz, the DUTY bit must be set in order to reach the 400 kHz maximum I2C frequency.
Page 756: C Fltr Register (I2C_Fltr)
Inter-integrated circuit (I C) interface RM0402 Bits 15:6 Reserved, must be kept at reset value Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode) These bits should provide the maximum duration of the SCL feedback loop in master mode. The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
Page 757: I2C Register Map
RM0402 Inter-integrated circuit (I C) interface 24.6.11 C register map The table below provides the I C register map and reset values. Table 135. I C register map and reset values Offset Register I2C_CR1 0x00 Reset value I2C_CR2 FREQ[5:0] 0x04 Reset value ADD[ I2C_OAR1...
Page 758: Universal Synchronous Receiver Transmitter (Usart) /Universal Asynchronous Receiver Transmitter (Uart)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) 25.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
Page 759: Usart Main Features
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 25.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance •...
Page 760: Usart Implementation
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- – Receive data register full – Idle line received – Overrun error – Framing error – Noise error – Parity error • Multiprocessor communication - enter into mute mode if address match does not occur •...
Page 761 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 762: Figure 245. Usart Block Diagram
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 245. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block...
Page 763: Usart Character Description
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 25.4.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 246). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame that contains data (The number of “1”...
Page 764: Transmitter
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 25.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.
Page 765: Figure 247. Configurable Stop Bits
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 247. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse...
Page 766: Figure 248. Tc/Txe Behavior When Transmitting
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 767: Receiver
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 25.4.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized.
Page 768 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Procedure: Enable the USART by writing the UE bit in USART_CR1 register to 1. Program the M bit in USART_CR1 to define the word length. Program the number of stop bits in USART_CR2. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take place.
Page 769 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
Page 770: Figure 250. Data Sampling When Oversampling By 16
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options: • the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set •...
Page 771: Table 137. Noise Detection From Sampled Data
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 251. Data sampling when oversampling by 8 RX line sampled values Sample clock (x8) One bit time MSv31153V1 Table 137. Noise detection from sampled data Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de-...
Page 772: Fractional Baud Rate Generation
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected.
Page 773 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Fraction (USARTDIV) = 12/16 = 0d0.75 Therefore USARTDIV = 0d27.75 Example 2: To program USARTDIV = 0d25.62 This leads to: DIV_Fraction = 16*0d0.62 = 0d9.92 The nearest real number is 0d10 = 0xA DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19 Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625 Example 3:...
Page 774: Table 138. Error Calculation For Programmed Baud Rates At F
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x0330 =>...
Page 775 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 139. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK...
Page 776 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 141. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 16 MHz = 24 MHz PCLK PCLK...
Page 777 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 142. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
Page 778 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 144. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
Page 779 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 145. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK...
Page 780 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 146. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK...
Page 781 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Table 147. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK...
Page 782: Usart Receiver Tolerance To Clock Deviation
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Table 149. Error calculation for programmed baud rates at f = 100 MHz or f = 50 MHz, PCLK PCLK (1)(2) oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 100 MHz = 50 MHz PCLK PCLK...
Page 783: Multiprocessor Communication
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver The USART receiver tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices: • 10- or 11-bit character length defined by the M bit in the USART_CR1 register •...
Page 784: Figure 252. Mute Mode Using Idle Line Detection
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Idle line detection (WAKE=0) The USART enters mute mode when the RWU bit is written to 1. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register.
Page 785: Parity Control
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 253. Mute mode using address mark detection In this example, the current address of the receiver is 1 (programmed in the USART_CR2 register) RXNE RXNE RXNE IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5 Mute mode...
Page 786: Lin (Local Interconnection Network) Mode
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- sequence (a read from the status register followed by a read or write access to the USART_DR data register). Note: In case of wakeup by an address mark: the MSB bit of the data is taken into account to identify an address but not the parity bit.
Page 787: Figure 254. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver detection circuit receives either a ‘1, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown in Figure 254.
Page 788: Usart Synchronous Mode
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 255. Break detection in LIN mode vs. Framing error detection Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header) 1 data time 1 data time RXNE /FE LBDF...
Page 789: Figure 256. Usart Example Of Synchronous Transmission
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 790: Single-Wire Half-Duplex Communication
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 258. USART data clock timing diagram (M=1) Idle or Idle or next preceding Start M bits =01 (9 data bits) Stop transmission transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1)
Page 791: Smartcard
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception.
Page 792: Figure 261. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame.
Page 793: Irda Sir Endec Block
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 25.4.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •...
Page 794: Figure 262. Irda Sir Endec- Block Diagram
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate that can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <...
Page 795: Continuous Communication Using Dma
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 25.4.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register.
Page 796: Figure 264. Transmission Using Dma
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 264. Transmission using DMA Idle preamble Frame 2 Frame 1 Frame 3 TX line Set by hardware Set by hardware TXE flag cleared by DMA read Set by hardware cleared by DMA read Ignored by the DMA because DMA request the transfer is complete...
Page 797: Hardware Flow Control
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Figure 265. Reception using DMA Frame 2 Frame 1 Frame 3 TX line Set by hardware RXNE flag cleared by DMA read DMA request USART_TDR DMA reads USART_TDR Cleared DMA TCIF flag Set by hardware (transfer complete) software...
Page 798: Figure 267. Rts Flow Control
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.
Page 799: Usart Interrupts
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Note: Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the nCTS input state to send a break. 25.5 USART interrupts Table 153. USART interrupt requests Interrupt event Event flag Enable control bit...
Page 800: Usart Registers
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Figure 269. USART interrupt mapping diagram TCIE TXEIE CTSIE IDLE IDLEIE RXNEIE RXNEIE USART RXNE interrupt PEIE LBDIE DMAR MS35853V1 25.6 USART registers Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits).
Page 801 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
Page 802 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
Page 803: Data Register (Usart_Dr)
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver 25.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 804: Control Register 1 (Usart_Cr1)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 25.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVER8 Res. WAKE PEIE TXEIE TCIE...
Page 805 RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever PE=1 in the USART_SR register Bit 7 TXEIE: TXE interrupt enable This bit is set and cleared by software.
Page 806: Control Register 2 (Usart_Cr2)
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 25.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINEN STOP[1:0] CLKEN CPOL CPHA...
Page 807: Control Register 3 (Usart_Cr3)
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 808 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
Page 809: Guard Time And Prescaler Register (Usart_Gtpr)
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
Page 810: Usart Register Map
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit- 25.6.8 USART register map The table below gives the USART register map and reset values. Table 154. USART register map and reset values Offset Register USART_SR 0x00 Reset value USART_DR DR[8:0] 0x04 Reset value DIV_Fraction...
Page 811: Serial Peripheral Interface/ Inter-Ic Sound (Spi/I2S)
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
Page 812: Spi Main Features
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.1.1 SPI main features • Master or slave operation • Full-duplex synchronous transfers on three lines • Half-duplex synchronous transfer on two lines (with bidirectional data line) • Simplex synchronous transfers on two lines (with unidirectional data line) •...
Page 813: Spi Extended Features
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.1.2 SPI extended features • SPI TI mode support 26.1.3 I2S features • Full-duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 814: Spi Functional Description
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.3 SPI functional description 26.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 270.
Page 815: Communications Between One Master And One Slave
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 816: Figure 272. Half-Duplex Single Master/ Single Slave Application
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 272. Half-duplex single master/ single slave application MISO MISO Rx shift register Tx shift register 1kΩ MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave MSv39624V1 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 817: Figure 273. Simplex Single Master/Single Slave Application
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 273. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) MISO MISO Rx shift register Tx shift register MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave MSv39625V1...
Page 818: Standard Multi-Slave Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 274.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Page 819: Multi-Master Communication
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time.
Page 820: Figure 276. Hardware/Software Slave Select Management
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0).
Page 821: Communication Formats
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format.
Page 822: Figure 277. Data Clock Timing Diagram
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 277. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO LSBit MSBit (to slave) Capture strobe CPHA =0 CPOL = 1 CPOL = 0 MOSI LSBit MSBit MISO...
Page 823: Spi Configuration
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
Page 824: Data Transmission And Reception Procedures
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted. A read access to the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer.
Page 825: Figure 278. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) underflow error signal for slave operating in SPI mode, and that data from the slave are always transacted and processed by the master even if the slave cannot not prepare them correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high.
Page 826: Procedure For Disabling The Spi
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 279. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers Example in Slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 827: Communication Using Dma (Direct Memory Addressing)
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data.
Page 828: Figure 280. Transmission Using Dma
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used.
Page 829: Spi Status Flags
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 281. Reception using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware clear by DMA read RXNE flag...
Page 830: Spi Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •...
Page 831: Spi Special Features
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value.
Page 832: Crc Calculation
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set.
Page 833 RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
Page 834: Spi Interrupts
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.5 SPI interrupts During SPI communication an interrupts can be generated by the following events: • Transmit Tx buffer ready to be loaded • Data received in Rx buffer • Master mode fault •...
Page 835: S Functional Description
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.6 S functional description 26.6.1 S general description The block diagram of the I S is shown in Figure 283. Figure 283. I S block diagram Address and data bus Tx buffer BSY OVR MODF TxE RxNE SIDE 16-bit...
Page 836: I2S Full-Duplex
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 The SPI can function as an audio I S interface when the I S capability is enabled (by setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins, flags and interrupts as the SPI.
Page 837: Supported Audio Protocols
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) I2Sx can operate in master mode. As a result: • Only I2Sx can output SCK and WS in half-duplex mode • Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full-duplex mode. The extended I2Ss (I2Sx_ext) can be used only in full-duplex mode.
Page 838: Figure 285. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 285. I S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) transmission reception Can be 16-bit or 32-bit Channel left Channel right MS19591V1 Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 839: Figure 288. Receiving 0X8Eaa33
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 288. Receiving 0x8EAA33 First read to Data register Second read to Data register 0x8EAA 0x33XX Only the 8 MSB are sent to compare the 24 bits 8 LSBs have no meaning and can be anything MS19594V1 Figure 289.
Page 840: Figure 291. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 291. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 Transmission Reception 16- or 32 bit data Channel left Channel right MS30100 V1 Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge (for the receiver).
Page 841: Figure 294. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 294. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 Reception Transmission 16- or 32-bit data Channel left Channel right MS30103V1 Figure 295. LSB justified 24-bit frame length with CPOL = 0 Reception Transmission 8-bit data...
Page 842: Figure 297. Operations Required To Receive 0X3478Ae
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 297. Operations required to receive 0x3478AE First read from Data register Second read from Data register conditioned by RXNE=1 conditioned by RXNE=1 0xXX34 0x78AE Only the 8 LSB of the half-word are significant. A field of 0x00 is forced instead of the 8 MSBs.
Page 843: Clock Generator
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPIx_I2SCFGR register. Figure 300.
Page 844: Figure 302. Audio Sampling Frequency Definition
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Figure 302. Audio sampling frequency definition 16-or 32-bit 16-or 32-bit left right channel channel 32- or 64-bits sampling point sampling point : audio sampling frequency MS30108V1 When the master mode is configured, a specific action needs to be taken to properly program the linear divider in order to communicate with the desired audio frequency.
Page 845: Table 157. Audio-Frequency Precision Using Standard 8 Mhz Hse
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Table 157. Audio-frequency precision using standard 8 MHz HSE SYSCLK Data Target f I2SDIV I2SODD MCLK Real f (KHz) Error length (Hz) (MHz) 96000 93750 2.3438% 96000 93750 2.3438% 48000 48387.0968 0.8065% 48000 46875 2.3438% 44100...
Page 846: I 2 S Master Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.6.5 S master mode The I S can be configured as follows: • In master mode for transmission or reception (half-duplex mode using I2Sx) • In master mode transmission and reception (full-duplex mode using I2Sx and I2Sx_ext).
Page 847 RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. To switch off the I S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.
Page 848: I 2 S Slave Mode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.6.6 S slave mode The I S can be configured as follows: • In slave mode for transmission or reception (half-duplex mode using I2Sx) • In slave mode transmission and reception (full-duplex mode using I2Sx and I2Sx_ext). The operating mode is following mainly the same rules as described for the I S master configuration.
Page 849: I 2 S Status Flags
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. An underrun flag is set and an interrupt may be generated if the data are not written into the SPIx_DR register before the first clock edge of the next data communication.
Page 850: I 2 S Error Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 The BSY flag is cleared: • When a transfer completes (except in master transmit mode, in which the communication is supposed to be continuous) • When the I S is disabled When communication is continuous: •...
Page 851: I 2 S Interrupts
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in the SPIx_CR2 register.
Page 852: Spi And I 2 S Registers
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
Page 853 RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 11 DFF: Data frame format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. It is not used in I S mode.
Page 854: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 855: Spi Status Register (Spi_Sr)
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment.
Page 856 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 26.4 on page 831 for the software sequence.
Page 857: Spi Data Register (Spi_Dr)
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 858: Spi Rx Crc Register (Spi_Rxcrcr) (Not Used In I 2 S Mode)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 859: Spi_I 2 S Configuration Register (Spi_I2Scfgr)
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) 26.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 ASTRE PCMSY Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN Bits 15:13 Reserved, must be kept at reset value. Bit 12 ASTREN: Asynchronous start enable.
Page 860: Spi_I 2 S Prescaler Register (Spi_I2Spr)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 26.6.3 on page 837.
Page 861 RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled. It is used only when the I S is in master mode.
Page 862: Spi Register Map
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402 26.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 159. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value...
Page 863: Secure Digital Input/Output Interface (Sdio)
RM0402 Secure digital input/output interface (SDIO) Secure digital input/output interface (SDIO) 27.1 SDIO main features The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The MultiMediaCard system specifications are available through the MultiMediaCard Association website, published by the MMCA technical committee.
Page 864: Figure 304. "No Response" And "No Data" Operations
Secure digital input/output interface (SDIO) RM0402 Figure 304. “No response” and “no data” operations From host to card(s) From host to card From card to host SDIO_CMD Command Command Response SDIO_D Operation (no response) Operation (no data) MSv36068V1 Figure 305. (Multiple) block read operation From host to card From card to host data from card to host Stop command...
Page 865: Sdio Functional Description
RM0402 Secure digital input/output interface (SDIO) Figure 307. Sequential read operation From host to card(s) From card to host Stop command stops data transfer Data from card to host SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation Data transfer operation MSv36071V1 Figure 308.
Page 866: Table 160. Sdio I/O Definitions
Secure digital input/output interface (SDIO) RM0402 By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used.
Page 867: Sdio Adapter
RM0402 Secure digital input/output interface (SDIO) 27.3.1 SDIO adapter Figure 310 shows a simplified block diagram of an SDIO adapter. Figure 310. SDIO adapter SDIO adapter SDIO_CK Control unit Command SDIO_CMD path Adapter registers To APB2 Data path SDIO_D[7:0] interface FIFO PCLK2 SDIOCLK...
Page 868: Figure 311. Control Unit
Secure digital input/output interface (SDIO) RM0402 Figure 311. Control unit Control unit Power management Adapter SDIO_CK Clock management registers To command and data path MSv36075V1 The control unit is illustrated in Figure 311. It consists of a power management subunit and a clock management subunit.
Page 869: Figure 313. Sdio Adapter Command Path
RM0402 Secure digital input/output interface (SDIO) Command path The command path unit sends commands to and receives responses from the cards. Figure 313. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDIO_CMDin Argument SDIO_CMDout Shift register...
Page 870: Figure 314. Command Path State Machine (Sdio)
Secure digital input/output interface (SDIO) RM0402 Figure 314. Command path state machine (SDIO) On reset CPSM enabled and pending command Idle CPSM disabled Response received or disabled or command Enabled and CRC failed command start Pend CPSM disabled or no response Last data CPSM disabled or Send...
Page 871: Table 161. Command Format
RM0402 Secure digital input/output interface (SDIO) Figure 315. SDIO command transfer at least 8 SDIO_CK cycles SDIO_CK Command Response Command State Idle Send Wait Receive Idle Send SDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives MSv36079V1 • Command format –...
Page 872: Table 162. Short Response Format
Secure digital input/output interface (SDIO) RM0402 Table 162. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 163. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 873: Figure 316. Data Path
RM0402 Secure digital input/output interface (SDIO) Data path The data path subunit transfers data to and from cards. Figure 316 shows a block diagram of the data path. Figure 316. Data path Data path Status Control Data To control unit flag logic timer...
Page 874: Figure 317. Data Path State Machine (Dpsm)
Secure digital input/output interface (SDIO) RM0402 Figure 317. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 875: Table 165. Data Token Format
RM0402 Secure digital input/output interface (SDIO) Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
Page 876: Table 166. Dpsm Flags
Secure digital input/output interface (SDIO) RM0402 DPSM Flags The status of the data path subunit transfer is reported by several status flags Table 166. DPSM flags Flag Description Set to high when data block send/receive CRC check is passed. DBCKEND In SDIO multibyte transfer mode this flag is set at the end of the transfer (a multibyte transfer is considered as a single block transfer by the host).
Page 877: Table 167. Transmit Fifo Status Flags
RM0402 Secure digital input/output interface (SDIO) Table 167. Transmit FIFO status flags Flag Description TXFIFOF Set to high when all 32 transmit FIFO words contain valid data. TXFIFOE Set to high when the transmit FIFO does not contain valid data. Set to high when 8 or more transmit FIFO words are empty.
Page 878: Sdio Apb2 Interface
Secure digital input/output interface (SDIO) RM0402 27.3.2 SDIO APB2 interface The APB2 interface generates the interrupt and DMA requests, and accesses the SDIO adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic. SDIO interrupts The interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high.
Page 879: Card Functional Description
RM0402 Secure digital input/output interface (SDIO) Example of write procedure using DMA Send CMD24 (WRITE_BLOCK) as follows: Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process) Program DMA channel (refer to DMA configuration for SDIO controller) Program the SDIO argument register with the address location of the card from...
Page 880: Card Reset
Secure digital input/output interface (SDIO) RM0402 27.4.2 Card reset The GO_IDLE_STATE command (CMD0) is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52) resets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high- impedance state and the cards are initialized with a default relative card address (RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability).
Page 881: Block Write
RM0402 Secure digital input/output interface (SDIO) addresses the card. The assigned card changes to the Standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull. The SDIO card host repeats steps 5 through 7 until it receives a timeout condition. For the SD card, the identification process starts at clock rate F , and the SDIO_CMD line output drives are push-pull drivers instead of open-drain.
Page 882: Block Read
Secure digital input/output interface (SDIO) RM0402 Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card begins writing and holds the SDIO_D line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command.
Page 883 RM0402 Secure digital input/output interface (SDIO) The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: 8 2 writebllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------ TAAC ×...
Page 884: Erase: Group Erase And Sector Erase
Secure digital input/output interface (SDIO) RM0402 27.4.8 Erase: group erase and sector erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in the CSD.
Page 885 RM0402 Secure digital input/output interface (SDIO) at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card ignores all LSBs below the group size. Mechanical write protect switch A mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card.
Page 886 Secure digital input/output interface (SDIO) RM0402 When a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. Send LOCK/UNLOCK (CMD42) with the appropriate data block size on the data line including the 16-bit CRC.
Page 887 RM0402 Secure digital input/output interface (SDIO) When the password is previously set (PWD_LEN is not 0), the card is locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Page 888: Card Status Register
Secure digital input/output interface (SDIO) RM0402 27.4.11 Card status register The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card status information (which may be stored in a local status register) to the host.
Page 889 RM0402 Secure digital input/output interface (SDIO) Table 169. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error An error in the sequence of erase ERASE_SEQ_ERROR ’1’= error commands occurred. ’0’= no error An invalid selection of erase groups for ERASE_PARAM ’1’= error erase occurred.
Page 890 Secure digital input/output interface (SDIO) RM0402 Table 169. Card status (continued) Clear Bits Identifier Type Value Description condition An erase sequence was cleared before executing because an out of erase ’0’= cleared ERASE_RESET sequence command was received ’1’= set (commands other than CMD35, CMD36, CMD38 or CMD13) 0 = Idle 1 = Ready...
Page 891: Sd Status Register
RM0402 Secure digital input/output interface (SDIO) 27.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits.
Page 892: Table 171. Speed Class Code Field
Secure digital input/output interface (SDIO) RM0402 Table 170. SD status (continued) Clear Bits Identifier Type Value Description condition Performance of move indicated by PERFORMANCE_ 1 [MB/s] step. 439: 432 (See below) MOVE (See below) Size of AU 431:428 AU_SIZE (See below) (See below) 427:424 Reserved Number of AUs to be erased at a...
Page 893: Table 172. Performance Move Field
RM0402 Secure digital input/output interface (SDIO) PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps. If the card does not move used RUs (recording units), Pm should be considered as infinity. Setting the field to FFh means infinity. Table 172.
Page 894: Table 175. Erase Size Field
Secure digital input/output interface (SDIO) RM0402 ERASE_SIZE This 16-bit field indicates N . When N numbers of AUs are erased, the timeout ERASE ERASE value is specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation.
Page 895: Sd I/O Mode
RM0402 Secure digital input/output interface (SDIO) Table 177. Erase offset field (continued) ERASE_OFFSET Value definition 2 [sec] 3 [sec] 27.4.13 SD I/O mode SD I/O interrupts To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin on the SD interface.
Page 896: Commands And Responses
Secure digital input/output interface (SDIO) RM0402 registers (IO_RW_EXTENDED, CMD53) to temporarily stall the data transfer while allowing the MMC/SD module to send commands to any function within the SD I/O device. To determine when a card supports the ReadWait protocol, the MMC/SD module must test capability bits in the internal card registers.
Page 897: Table 178. Block-Oriented Write Commands
RM0402 Secure digital input/output interface (SDIO) Command types Both application-specific and general commands are divided into the four following types: • broadcast command (BC): sent to all cards; no responses returned. • broadcast command with response (BCR): sent to all cards; responses received from all cards simultaneously.
Page 898: Table 179. Block-Oriented Write Protection Commands
Secure digital input/output interface (SDIO) RM0402 Table 179. Block-oriented write protection commands Response Type Argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit [31:0] data CMD28 ac of the addressed group. The properties of SET_WRITE_PROT address write protection are coded in the card-...
Page 899: Response Formats
RM0402 Secure digital input/output interface (SDIO) Table 181. I/O mode commands (continued) Response Type Argument Abbreviation Description index format CMD40 bcr [31:0] stuff bits GO_IRQ_STATE Places the system in the interrupt mode. CMD41 Reserved Table 182. Lock card Response Type Argument Abbreviation Description...
Page 900: R1 (Normal Response Command)
Secure digital input/output interface (SDIO) RM0402 27.5.1 R1 (normal response command) Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 901: R3 (Ocr Register)
RM0402 Secure digital input/output interface (SDIO) 27.5.4 R3 (OCR register) Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1. The level coding is as follows: restricted voltage windows = low, card busy = low. Table 186.
Page 902: R5 (Interrupt Request)
Secure digital input/output interface (SDIO) RM0402 Table 188. R4b response (continued) Bit position Width (bits Value Description Card is ready [38:36] Number of I/O functions [39:8] Argument field Present memory [34:32] Stuff bits [31:8] I/O ORC [7:1] Reserved End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands.
Page 903: Sdio I/O Card-Specific Operations
RM0402 Secure digital input/output interface (SDIO) Table 190. R6 response Bit position Width (bits) Value Description Start bit Transmission bit [45:40] ‘101000’ CMD40 [31:16] RCA [31:16] of winning card or of the host [39:8] Argument field [15:0] Not defined. May be used for IRQ data [7:1] CRC7 End bit...
Page 904: Sdio Read Wait Operation By Stopping Sdio_Ck
Secure digital input/output interface (SDIO) RM0402 27.6.2 SDIO read wait operation by stopping SDIO_CK If the SDIO card does not support the previous read wait method, the SDIO can perform a read wait by stopping SDIO_CK (SDIO_DCTRL is set just like in the method presented in Section 27.6.1, but SDIO_DCTRL[10] =1): DSPM stops the clock two SDIO_CK cycles after the end bit of the current received block and starts the clock again after the read wait start bit...
Page 905: Sdio Registers
RM0402 Secure digital input/output interface (SDIO) SDIOCLK are frozen, the APB2 interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated. To enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset Flow Control is disabled.
Page 906 Secure digital input/output interface (SDIO) RM0402 Bits 31:15 Reserved, must be kept at reset value. Bit 14 HWFC_EN: HW Flow Control enable 0b: HW Flow Control is disabled 1b: HW Flow Control is enabled When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt signals, see SDIO Status register definition in Section 27.8.11.
Page 907: Sdio Argument Register (Sdio_Arg)
RM0402 Secure digital input/output interface (SDIO) 27.8.3 SDIO argument register (SDIO_ARG) Address offset: 0x08 Reset value: 0x0000 0000 The SDIO_ARG register contains a 32-bit command argument, which is sent to a card as part of a command message. CMDARG[31:16] CMDARG[15:0] Bits 31:0 CMDARG: Command argument Command argument sent to a card as part of a command message.
Page 908: Sdio Command Response Register (Sdio_Respcmd)
Secure digital input/output interface (SDIO) RM0402 Bit 8 WAITINT: CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an interrupt request. Bits 7:6 WAITRESP: Wait for response bits They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response.
Page 909: Sdio Data Timer Register (Sdio_Dtimer)
RM0402 Secure digital input/output interface (SDIO) CARDSTATUSx[31:16] CARDSTATUSx[15:0] Bits 31:0 CARDSTATUSx: see Table 191. The Card Status size is 32 or 127 bits, depending on the response type. Table 191. Response type and SDIO_RESPx registers Register Short response Long response SDIO_RESP1 Card Status[31:0] Card Status [127:96]...
Page 910: Sdio Data Length Register (Sdio_Dlen)
Secure digital input/output interface (SDIO) RM0402 27.8.8 SDIO data length register (SDIO_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. Res.
Page 911 RM0402 Secure digital input/output interface (SDIO) Bits 31:12 Reserved, must be kept at reset value. Bit 11 SDIOEN: SD I/O enable functions If this bit is set, the DPSM performs an SD I/O-card-specific operation. Bit 10 RWMOD: Read wait mode 0: Read Wait control stopping SDIO_D2 1: Read Wait control using SDIO_CK Bit 9 RWSTOP: Read wait stop...
Page 912 Secure digital input/output interface (SDIO) RM0402 Note: After a data write, data cannot be written to this register for three SDIOCLK clock periods plus two PCLK2 clock periods. The meaning of the DTMODE bit changes according to the value of the SDIOEN bit. When SDIOEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled, and when SDIOEN=1 and DTMODE=1, the peripheral enables an SDIO multibyte transfer.
Page 913: Sdio Data Counter Register (Sdio_Dcount)
RM0402 Secure digital input/output interface (SDIO) 27.8.10 SDIO data counter register (SDIO_DCOUNT) Address offset: 0x30 Reset value: 0x0000 0000 The SDIO_DCOUNT register loads the value from the data length register (see SDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0.
Page 914: Sdio Interrupt Clear Register (Sdio_Icr)
Secure digital input/output interface (SDIO) RM0402 Bit 20 TXDAVL: Data available in transmit FIFO Bit 19 RXFIFOE: Receive FIFO empty Bit 18 TXFIFOE: Transmit FIFO empty When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words. Bit 17 RXFIFOF: Receive FIFO full When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.
Page 915 RM0402 Secure digital input/output interface (SDIO) SDIO Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBCK DATA DTIME CTIME DCRC CCRC Res. Res. Res. Res. Res. Res. REND OVERR UNDERR ENDC ENDC SENTC OUTC OUTC FAILC...
Page 916: Sdio Mask Register (Sdio_Mask)
Secure digital input/output interface (SDIO) RM0402 Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag. 0: CTIMEOUT not cleared 1: CTIMEOUT cleared Bit 1 DCRCFAILC: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag. 0: DCRCFAIL not cleared 1: DCRCFAIL cleared Bit 0 CCRCFAILC: CCRCFAIL flag clear bit...
Page 917 RM0402 Secure digital input/output interface (SDIO) Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty. 0: Rx FIFO empty interrupt disabled 1: Rx FIFO empty interrupt enabled Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty.
Page 918: Sdio Fifo Counter Register (Sdio_Fifocnt)
Secure digital input/output interface (SDIO) RM0402 Bit 8 DATAENDIE: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0: Data end interrupt disabled 1: Data end interrupt enabled Bit 7 CMDSENTIE: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command.
Page 919: Sdio Data Fifo Register (Sdio_Fifo)
RM0402 Secure digital input/output interface (SDIO) Res. Res. Res. Res. Res. Res. Res. Res. FIFOCOUNT[23:16] FIFOCOUNT[15:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 FIFOCOUNT: Remaining number of words to be written to or read from the FIFO. 27.8.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80...
Page 920: Sdio Register Map
Secure digital input/output interface (SDIO) RM0402 27.8.16 SDIO register map The following table summarizes the SDIO registers. Table 192. SDIO register map Offset Register SDIO_ POWER 0x00 Reset value SDIO_ CLKCR 0x04 Reset value SDIO_ARG CMDARG 0x08 Reset value SDIO_CMD 0x0C Reset value SDIO_...
Page 921 RM0402 Secure digital input/output interface (SDIO) Table 192. SDIO register map (continued) Offset Register SDIO_ DATACOUNT DCOUNT 0x30 Reset value SDIO_STA 0x34 Reset value SDIO_ICR 0x38 Reset value SDIO_ MASK 0x3C Reset value SDIO_ FIFOCOUNT FIFOCNT 0x48 Reset value SDIO_FIFO FIF0Data 0x80 Reset value...
Page 922: Controller Area Network (Bxcan)
Controller area network (bxCAN) RM0402 Controller area network (bxCAN) 28.1 Introduction The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages.
Page 923: Bxcan General Description
RM0402 Controller area network (bxCAN) 28.3 bxCAN general description In today CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (to be handled by each node) has significantly increased. In addition to the application messages, Network Management and Diagnostic messages have been introduced.
Page 924: Acceptance Filters
Controller area network (bxCAN) RM0402 28.3.4 Acceptance filters The bxCAN provides up to 28 scalable/configurable identifier filter banks in dual CAN configuration, for selecting the incoming messages, that the software needs and discarding the others. Receive FIFO Two receive FIFOs are used by hardware to store the incoming messages. Three complete messages can be stored in each FIFO.
Page 925: Bxcan Operating Modes
RM0402 Controller area network (bxCAN) 28.4 bxCAN operating modes bxCAN has three main operating modes: initialization, normal and Sleep. After a hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pull- up is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode by setting the INRQ or SLEEP bits in the CAN_MCR register.
Page 926: Sleep Mode (Low-Power)
Controller area network (bxCAN) RM0402 28.4.3 Sleep mode (low-power) To reduce power consumption, bxCAN has a low-power mode called Sleep mode. This mode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In this mode, the bxCAN clock is stopped, however software can still access the bxCAN mailboxes.
Page 927: Test Mode
RM0402 Controller area network (bxCAN) 28.5 Test mode Test mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits must be configured while bxCAN is in Initialization mode. Once test mode has been selected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode. 28.5.1 Silent mode The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register.
Page 928: Loop Back Combined With Silent Mode
Controller area network (bxCAN) RM0402 This mode is provided for self-test functions. To be independent of external events, the CAN Core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal feedback from its Tx output to its Rx input.
Page 929 RM0402 Controller area network (bxCAN) mailbox starts (enter transmit state) when the CAN bus becomes idle. Once the mailbox has been successfully transmitted, it becomes empty again. The hardware indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR register. If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.
Page 930: Time Triggered Communication Mode
Controller area network (bxCAN) RM0402 Figure 324. Transmit mailbox states EMPTY RQCP=X TXOK=X TXRQ=1 TME = 1 PENDING Mailbox has RQCP=0 TXOK=0 highest priority ABRQ=1 TME = 0 Mailbox does not have highest priority EMPTY SCHEDULED RQCP=0 RQCP=1 ABRQ=1 TXOK=0 TXOK=0 TME = 0 TME = 1...
Page 931: Figure 325. Receive Fifo States
RM0402 Controller area network (bxCAN) Figure 325. Receive FIFO states EMPTY Valid Message FMP=0x00 FOVR=0 Received PENDING_1 Release FMP=0x01 Mailbox FOVR=0 Valid Message Release Received Mailbox RFOM=1 PENDING_2 FMP=0x10 FOVR=0 Valid Message Release Mailbox Received RFOM=1 PENDING_3 Valid Message FMP=0x11 FOVR=0 Received OVERRUN...
Page 932: Identifier Filtering
Controller area network (bxCAN) RM0402 Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception leads to an overrun and a message is lost. The hardware signals the overrun condition by setting the FOVR bit in the CAN_RFR register. Which message is lost depends on the configuration of the FIFO: •...
Page 933 RM0402 Controller area network (bxCAN) Identifier list mode In identifier list mode, the mask registers are used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers. All bits of the incoming identifier must match the bits specified in the filter registers.
Page 934: Figure 326. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0402 Figure 326. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mask CAN_FxR2[31:24] CAN_FxR2[23:16] CAN_FxR2[15:8] CAN_FxR2[7:0] Mapping STD ID STID[10:3] STID[2:0] Mapping Ext ID EXID[20:13] EXTID[28:21] EXID[12:5] EXID[4:0]...
Page 935: Figure 327. Example Of Filter Numbering
RM0402 Controller area network (bxCAN) The index value of the filter number does not take into account the activation state of the filter banks. In addition, two independent numbering schemes are used, one for each FIFO. Refer to Figure 327 for an example.
Page 936: Message Storage
Controller area network (bxCAN) RM0402 Figure 328. Filtering mechanism - example Example of 3 filter banks in 32-bit unidentified mode and the remaining in 32-bit identifier mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier Identifier #4 Match...
Page 937: Table 193. Transmit Mailbox Mapping
RM0402 Controller area network (bxCAN) Table 193. Transmit mailbox mapping Offset to transmit mailbox base address Register name CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 938: Error Management
Controller area network (bxCAN) RM0402 28.7.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 939: Figure 330. Bit Timing
RM0402 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 940: Figure 331. Can Frames
Controller area network (bxCAN) RM0402 Figure 331. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard Identifier) or Overload Frame 44 + 8 *N ACK Field Arbitration Field Ctrl Field Data Field CRC Field 8 *N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame 64 + 8 *N...
Page 941: Bxcan Interrupts
RM0402 Controller area network (bxCAN) 28.8 bxCAN interrupts Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER). Figure 332. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT...
Page 942: Can Registers
Controller area network (bxCAN) RM0402 • The transmit interrupt can be generated by the following events: – Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set. – Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set. –...
Page 943 RM0402 Controller area network (bxCAN) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Bits 31:17 Reserved, must be kept at reset value. Bit 16 DBF: Debug freeze 0: CAN working during debug 1: CAN reception/transmission frozen during debug.
Page 944 Controller area network (bxCAN) RM0402 Bit 3 RFLM Receive FIFO locked mode 0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next incoming message overwrites the previous one. 1: Receive FIFO locked against overrun. Once a receive FIFO is full the next incoming message is discarded.
Page 945 RM0402 Controller area network (bxCAN) Bit 8 TXM Transmit mode The CAN hardware is currently transmitter. Bits 7:5 Reserved, must be kept at reset value. Bit 4 SLAKI Sleep acknowledge interrupt When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered Sleep Mode.
Page 946 Controller area network (bxCAN) RM0402 Bit 31 LOW2 Lowest priority flag for mailbox 2 This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. Bit 30 LOW1 Lowest priority flag for mailbox 1 This bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority.
Page 947 RM0402 Controller area network (bxCAN) Bit 11 TERR1 Transmission error of mailbox1 This bit is set when the previous TX failed due to an error. Bit 10 ALST1 Arbitration lost for mailbox1 This bit is set when the previous TX failed due to an arbitration lost. Bit 9 TXOK1 Transmission OK of mailbox1 The hardware updates this bit after each transmission attempt.
Page 948 Controller area network (bxCAN) RM0402 Bits 31:6 Reserved, must be kept at reset value. Bit 5 RFOM0 Release FIFO 0 output mailbox Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO. Setting this bit when the FIFO is empty has no effect.
Page 949 RM0402 Controller area network (bxCAN) Bit 3 FULL1 FIFO 1 full Set by hardware when three messages are stored in the FIFO. This bit is cleared by software. Bit 2 Reserved, must be kept at reset value. Bits 1:0 FMP1[1:0] FIFO 1 message pending These bits indicate how many messages are pending in the receive FIFO1.
Page 950 Controller area network (bxCAN) RM0402 Bit 7 Reserved, must be kept at reset value. Bit 6 FOVIE1 FIFO overrun interrupt enable 0: No interrupt when FOVR is set. 1: Interrupt generation when FOVR is set. Bit 5 FFIE1 FIFO full interrupt enable 0: No interrupt when FULL bit is set.
Page 951 RM0402 Controller area network (bxCAN) Bits 6:4 LEC[2:0] Last error code This field is set by hardware and holds a code which indicates the error condition of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field is cleared to 0.
Page 952: Can Mailbox Registers
Controller area network (bxCAN) RM0402 Bits 25:24 SJW[1:0] Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization. x (SJW[1:0] + 1) Bit 23 Reserved, must be kept at reset value. Bits 22:20 TS2[2:0] Time segment 2 These bits define the number of time quanta in Time Segment 2.
Page 953 RM0402 Controller area network (bxCAN) This register also implements the TX request control (bit 0) - reset value 0. STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] TXRQ Bits 31:21 STID[10:0]/EXID[28:18] Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Page 954 Controller area network (bxCAN) RM0402 CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX TIME[15:0] Res.
Page 955 RM0402 Controller area network (bxCAN) CAN mailbox data low register (CAN_TDLxR) (x = 0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: 0xXXXX XXXX DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]...
Page 956 Controller area network (bxCAN) RM0402 Bits 31:24 DATA7[7:0] Data byte 7 Data byte 7 of the message. Note: If TGT of this message and TTCM are active, DATA7 and DATA6 are replaced by the TIME stamp value. Bits 23:16 DATA6[7:0] Data byte 6 Data byte 6 of the message.
Page 957 RM0402 Controller area network (bxCAN) CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x = 0..1) Address offsets: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX All RX registers are write protected. TIME[15:0] FMI[7:0] Res. Res. Res. Res. DLC[3:0] Bits 31:16 TIME[15:0] Message time stamp...
Page 958 Controller area network (bxCAN) RM0402 CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX All RX registers are write protected.
Page 959: Can Filter Registers
RM0402 Controller area network (bxCAN) Bits 23:16 DATA6[7:0] Data Byte 6 Data byte 2 of the message. Bits 15:8 DATA5[7:0] Data Byte 5 Data byte 1 of the message. Bits 7:0 DATA4[7:0] Data Byte 4 Data byte 0 of the message. 28.9.4 CAN filter registers CAN filter master register (CAN_FMR)
Page 960 Controller area network (bxCAN) RM0402 Res. Res. Res. Res. FBM27 FBM26 FBM25 FBM24 FBM23 FBM22 FBM21 FBM20 FBM19 FBM18 FBM17 FBM16 FBM15 FBM14 FBM13 FBM12 FBM11 FBM10 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 Note: Refer to Figure 326: Filter bank scale configuration - register organization on page 934.
Page 961 RM0402 Controller area network (bxCAN) Res. Res. Res. Res. FFA27 FFA26 FFA25 FFA24 FFA23 FFA22 FFA21 FFA20 FFA19 FFA18 FFA17 FFA16 FFA15 FFA14 FFA13 FFA12 FFA11 FFA10 FFA9 FFA8 FFA7 FFA6 FFA5 FFA4 FFA3 FFA2 FFA1 FFA0 Bits 31:28 Reserved, must be kept at reset value. Bits 27:0 FFAx Filter FIFO assignment for filter x The message passing through this filter is stored in the specified FIFO.
Page 962 Controller area network (bxCAN) RM0402 Filter bank i register x (CAN_FiRx) (i = 0..27, x = 1, 2) Address offsets: 0x240 to 0x31C Reset value: 0xXXXX XXXX There are 28 filter banks, i= 0 to 27. Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1].
Page 963: Bxcan Register Map
RM0402 Controller area network (bxCAN) 28.9.5 bxCAN register map Refer to Section 2.2 on page 49 for the register boundary addresses. The registers from offset 0x200 to 0x31C are present only in CAN1. Table 195. bxCAN register map and reset values Offset Register CAN_MCR...
Page 964 Controller area network (bxCAN) RM0402 Table 195. bxCAN register map and reset values (continued) Offset Register CAN_TDT0R TIME[15:0] DLC[3:0] 0x184 - - - - - - - - - - - Reset value CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x188 Reset value CAN_TDH0R DATA7[7:0] DATA6[7:0]...
Page 965 RM0402 Controller area network (bxCAN) Table 195. bxCAN register map and reset values (continued) Offset Register CAN_RDT0R TIME[15:0] FMI[7:0] DLC[3:0] 0x1B4 - - - - Reset value CAN_RDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x1B8 Reset value CAN_RDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x1BC Reset value CAN_RI1R...
Page 966 Controller area network (bxCAN) RM0402 Table 195. bxCAN register map and reset values (continued) Offset Register CAN_FA1R FACT[27:0] 0x21C Reset value 0x220 0x224- 0x23F CAN_F0R1 FB[31:0] 0x240 Reset value CAN_F0R2 FB[31:0] 0x244 Reset value CAN_F1R1 FB[31:0] 0x248 Reset value CAN_F1R2 FB[31:0] 0x24C Reset value...
Page 967: Usb On-The-Go Full-Speed (Otg_Fs)
RM0402 USB on-the-go full-speed (OTG_FS) USB on-the-go full-speed (OTG_FS) 29.1 Introduction Portions Copyright (c) Synopsys, Inc. All rights reserved. Used with permission. This section presents the architecture and the programming model of the OTG_FS controller. The following acronyms are used throughout the section: Full-speed Low-speed Media access controller...
Page 968: Otg_Fs Main Features
USB on-the-go full-speed (OTG_FS) RM0402 29.2 OTG_FS main features The main features can be divided into three categories: general, host-mode and device- mode features. 29.2.1 General features The OTG_FS interface general features are the following: • It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 •...
Page 969: Host-Mode Features
RM0402 USB on-the-go full-speed (OTG_FS) 29.2.2 Host-mode features The OTG_FS interface main features and requirements in host-mode are the following: • External charge pump for V voltage generation. • Up to 12 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer.
Page 970: Otg_Fs Implementation
USB on-the-go full-speed (OTG_FS) RM0402 29.3 OTG_FS implementation Table 197. OTG_FS implementation USB features OTG_FS Device bidirectional endpoints (including EP0) Host mode channels Size of dedicated SRAM 1.2 KBytes USB 2.0 link power management (LPM) support OTG revision supported Attach detection protocol (ADP) support Battery charging detection (BCD) support 1.
Page 971: Otg_Fs Functional Description
RM0402 USB on-the-go full-speed (OTG_FS) 29.4 OTG_FS functional description 29.4.1 OTG_FS block diagram Figure 334. OTG_FS full-speed block diagram ® Cortex core OTG_FS_DP Power USB2.0 OTG_FS_DM OTG FS UTMIFS clock OTG_FS_ID core controller USB suspend OTG_FS_VBUS USB clock USB clock at 48 MHz System clock domain domain Universal serial bus...
Page 972: Otg_Fs Core
USB on-the-go full-speed (OTG_FS) RM0402 Table 199. OTG_FS input/output signals Signal name Signal type Description usb_sof Digital output USB OTG start-of-frame event for on chip peripherals usb_wkup Digital output USB OTG wakeup event output usb_gbl_it Digital output USB OTG global interrupt 29.4.3 OTG_FS core The USB OTG_FS receives the 48 MHz clock from the reset and clock controller (RCC).
Page 973: Otg Detections
RM0402 USB on-the-go full-speed (OTG_FS) 29.4.5 OTG detections Additionally the OTG_FS uses the following functions: • integrated ID pull-up resistor used to sample the ID line for A/B device identification. • sensing comparators with hysteresis used to detect V valid, A-B session valid and session-end voltage thresholds.
Page 974: Hnp Dual Role Device
USB on-the-go full-speed (OTG_FS) RM0402 29.5.2 HNP dual role device The HNP capable bit in the Global USB configuration register (HNPCAP bit in OTG_ GUSBCFG) enables the OTG_FS core to dynamically change its role from A-host to A- peripheral and vice-versa, or from B-Peripheral to B-host and vice-versa according to the host negotiation protocol (HNP).
Page 975: Srp-Capable Peripheral
RM0402 USB on-the-go full-speed (OTG_FS) Figure 336. OTG_FS peripheral-only connection 5 V to V Voltage regulator STMPS2141STR GPIO Current-limited 5 V Pwr Overcurrent power distribution GPIO + IRQ switch VBUS OSC_IN OSC_OUT MSv36916V2 1. Use a regulator to build a bus-powered device. 29.6.1 SRP-capable peripheral The SRP capable bit in the Global USB configuration register (SRPCAP bit in...
Page 976: Peripheral Endpoints
USB on-the-go full-speed (OTG_FS) RM0402 Soft disconnect The powered state can be exited by software with the soft disconnect feature. The DP pull- up resistor is removed by setting the soft disconnect bit in the device control register (SDIS bit in OTG_DCTL), causing a device disconnect detection interrupt on the host side even though the USB cable was not really removed from the host port.
Page 977 RM0402 USB on-the-go full-speed (OTG_FS) which the transfer is not completed in the current frame. This interrupt is asserted along with the end of periodic frame interrupt (OTG_GINTSTS/EOPF). • 5 OUT endpoints – Each of them can be configured to support the isochronous, bulk or interrupt transfer type –...
Page 978: Otg_Fs As A Usb Host
USB on-the-go full-speed (OTG_FS) RM0402 the core interrupt register (OEPINT bit in OTG_GINTSTS or IEPINT bit in OTG_GINTSTS, respectively) is set. Before the application can read these registers, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register.
Page 979: Srp-Capable Host
RM0402 USB on-the-go full-speed (OTG_FS) Figure 337. OTG_FS host-only connection STMPS2141STR GPIO Current-limited 5 V Pwr power distribution Overcurrent GPIO + IRQ switch VBUS OSC_IN OSC_OUT MSv36915V2 1. V range is between 2 V and 3.6 V. 29.7.1 SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration register (SRPCAP bit in OTG_GUSBCFG).
Page 980 USB on-the-go full-speed (OTG_FS) RM0402 Host detection of a peripheral connection If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_FS does not detect any bus connection until V is no longer sensed at a valid level (5 V).
Page 981: Host Channels
RM0402 USB on-the-go full-speed (OTG_FS) 29.7.3 Host channels The OTG_FS core instantiates 12 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 12 transfer requests at the same time. If more than 12 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts.
Page 982: Host Scheduler
USB on-the-go full-speed (OTG_FS) RM0402 The mask bits for each interrupt source of each channel are also available in the OTG_HCINTMSKx register. • The host core provides the following status checks and interrupt generation: – Transfer completed interrupt, indicating that the data transfer is complete on both the application (AHB) and USB sides –...
Page 983: Otg_Fs Sof Trigger
RM0402 USB on-the-go full-speed (OTG_FS) PTXQSAV bits in the OTG_HNPTXSTS register or NPTQXSAV bits in the OTG_HNPTXSTS register. 29.8 OTG_FS SOF trigger Figure 338. SOF connectivity (SOF trigger output to TIM and ITR1 connection) STM32 SOF pulse output, to external audio control ITR1 SOF pulse SOFgen...
Page 984: Otg_Fs Low-Power Modes
USB on-the-go full-speed (OTG_FS) RM0402 The end of periodic frame interrupt (OTG_GINTSTS/EOPF) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_DCFG). This feature can be used to determine if all of the isochronous traffic for that frame is complete.
Page 985: Otg_Fs Dynamic Update Of The Otg_Hfir Register
RM0402 USB on-the-go full-speed (OTG_FS) the USB clock switching activity is cut even if the system clock is kept running by the application for other purposes. • USB system stop When the OTG_FS is in the USB suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system.
Page 986: Peripheral Fifo Architecture
USB on-the-go full-speed (OTG_FS) RM0402 29.11.1 Peripheral FIFO architecture Figure 340. Device-mode FIFO address mapping and AHB FIFO access mapping Single data FIFO IN endpoint Tx FIFO #x Dedicated Tx OTG_DIEPTXFx[31:16] Tx FIFO #x DFIFO push access FIFO #x control packet from AHB (optional)
Page 987: Host Fifo Architecture
RM0402 USB on-the-go full-speed (OTG_FS) Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the endpoint 0 transmit FIFO size register (OTG_DIEPTXF0) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (OTG_DIEPTXFx) for IN endpoint-x. 29.11.2 Host FIFO architecture Figure 341.
Page 988: Fifo Ram Allocation
USB on-the-go full-speed (OTG_FS) RM0402 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB.
Page 989 RM0402 USB on-the-go full-speed (OTG_FS) Device RxFIFO = (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK Example: The MPS is 1,024 bytes for a periodic USB packet and 512 bytes for a non- periodic USB packet.
Page 990: Otg_Fs System Performance
USB on-the-go full-speed (OTG_FS) RM0402 29.12 OTG_FS system performance Best USB and system performance is achieved owing to the large RAM buffers, the highly configurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and, especially, the advanced FIFO control mechanism. Indeed, this mechanism allows the OTG_FS to fill in the available RAM space at best regardless of the current USB sequence.
Page 991: Figure 342. Interrupt Hierarchy
RM0402 USB on-the-go full-speed (OTG_FS) Figure 342. Interrupt hierarchy Wakeup interrupt OTG_FS_WKUP Global interrupt OTG_FS Global interrupt mask (bit 0) OTG_AHBCFG AHB configuration register OTG_GINTSTS Core register interrupt 31:26 25 24 23:20 19 18 17:3 OTG_GINTMSK Core interrupt mask register OTG_GOTGINT OTG interrupt register (15 + #EP):16...
Page 992: Otg_Fs Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0402 29.14 OTG_FS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed by words (32 bits).
Page 993: Table 202. Host-Mode Control And Status Registers (Csrs)
RM0402 USB on-the-go full-speed (OTG_FS) Table 201. Core global control and status registers (CSRs) (continued) Address Acronym Register name offset Section 29.15.8: OTG receive status debug read register (OTG_GRXSTSR) OTG_GRXSTSR 0x01C Section 29.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) Section 29.15.10: OTG status read and pop registers (OTG_GRXSTSP) OTG_GRXSTSP 0x020...
Page 994: Table 203. Device-Mode Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0402 Table 202. Host-mode control and status registers (CSRs) (continued) Offset Acronym Register name address OTG_HPRT 0x440 Section 29.15.27: OTG host port control and status register (OTG_HPRT) 0x500 0x520 Section 29.15.28: OTG host channel x characteristics register OTG_HCCHARx (OTG_HCCHARx) 0x660...
Page 995 RM0402 USB on-the-go full-speed (OTG_FS) Table 203. Device-mode control and status registers (continued) Offset Acronym Register name address Section 29.15.42: OTG device IN endpoint FIFO empty interrupt mask OTG_DIEPEMPMSK 0x834 register (OTG_DIEPEMPMSK) Section 29.15.43: OTG device control IN endpoint 0 control register OTG_DIEPCTL0 0x900 (OTG_DIEPCTL0)
Page 996: Otg_Fs Registers
USB on-the-go full-speed (OTG_FS) RM0402 Data FIFO (DFIFO) access register map These registers, available in both host and device modes, are used to read or write the FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on the channel.
Page 997: Otg Control And Status Register (Otg_Gotgctl)
RM0402 USB on-the-go full-speed (OTG_FS) 29.15.1 OTG control and status register (OTG_GOTGCTL) Address offset: 0x000 Reset value: 0x0001 0000 The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. Res. Res. Res. Res. Res.
Page 998 USB on-the-go full-speed (OTG_FS) RM0402 Bits 15:13 Reserved, must be kept at reset value. Bit 12 EHEN: Embedded host enable It is used to select between OTG A device state machine and embedded host state machine. 0: OTG A device state machine is selected 1: Embedded host state machine is selected Bit 11 DHNPEN: Device HNP enabled The application sets this bit when it successfully receives a SetFeature.SetHNPEnable...
Page 999 RM0402 USB on-the-go full-speed (OTG_FS) Bit 4 AVALOEN: A-peripheral session valid override enable. This bit is used to enable/disable the software to override the Avalid signal using the AVALOVAL bit. 0:Override is disabled and Avalid signal from the respective PHY selected is used internally by the core 1:Internally Avalid received from the PHY is overridden with AVALOVAL bit value Note: Only accessible in host mode.
Page 1000: Otg Interrupt Register (Otg_Gotgint)
USB on-the-go full-speed (OTG_FS) RM0402 29.15.2 OTG interrupt register (OTG_GOTGINT) Address offset: 0x04 Reset value: 0x0000 0000 The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. ADTO Res.

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