ST STM32F40 Series Reference Manual page 731

Inter-integrated circuit (I
Bit 9 ITEVTEN: Event interrupt enable
Bit 8 ITERREN: Error interrupt enable
Bits 7:6 Reserved, must be kept at reset value
Bits 5:0 FREQ[5:0]: Peripheral clock frequency
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C) interface
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
–SB = 1 (Master)
–ADDR = 1 (Master/Slave)
–ADD10= 1 (Master)
–STOPF = 1 (Slave)
–BTF = 1 with no TxE or RxNE event
–TxE event to 1 if ITBUFEN = 1
–RxNE event to 1if ITBUFEN = 1
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
– BERR = 1
– ARLO = 1
– AF = 1
– OVR = 1
– PECERR = 1
– TIMEOUT = 1
– SMBALERT = 1
The peripheral clock frequency must be configured using the input APB clock frequency (I2C
peripheral connected to APB). The minimum allowed frequency is 2 MHz, the maximum
frequency is limited by the maximum APB frequency (42 MHz)and an intrinsic limitation of
46 MHz.
0b000000: Not allowed
0b000001: Not allowed
0b000010: 2 MHz
...
0b101010: 42MHz
Higher than 0b101010: Not allowed
Doc ID 018909 Rev 4
RM0090