Tim1&Tim8 Counter (Timx_Cnt); Tim1&Tim8 Prescaler (Timx_Psc); Tim1&Tim8 Auto-Reload Register (Timx_Arr) - ST STM32F40 Series Reference Manual

Advanced-control timers (TIM1&TIM8)
1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept
cleared.
Note: The state of the external I/O pins connected to the complementary OCx and OCxN
channels depends on the OCx and OCxN channel state and the GPIO registers.
14.4.10 TIM1&TIM8 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15 14 13
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Bits 15:0 CNT[15:0]: Counter value
14.4.11 TIM1&TIM8 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15 14 13
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Bits 15:0 ARR[15:0]: Auto-reload value
413/1422
12 11 10 9
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12 11 10 9
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The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
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ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 14.3.1: Time-base unit on page 356
and behavior.
The counter is blocked while the auto-reload value is null.
Doc ID 018909 Rev 4
8 7 6 5
CNT[15:0]
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8 7 6 5
PSC[15:0]
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CK_PSC
8 7 6 5
ARR[15:0]
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for more details about ARR update
4 3 2 1
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4 3 2 1
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/ (PSC[15:0] + 1).
4 3 2 1
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RM0090
0
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0
rw
0
rw