Figure 306. Audio Sampling Frequency Definition; Figure 307. I S Clock Generator Architecture - ST STM32F40 Series Reference Manual

Serial peripheral interface (SPI)
It will be: I

Figure 306. Audio sampling frequency definition

When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 307. I
I2SxCLK
1. Where x could be 2 or 3.
Figure 306
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 125
Note: Other configurations are possible that allow optimum clock precision.
829/1422
2
S bitrate = 32 x 2 x F
16-bit or 32-bit Left channel
sampling point
F : Audio sampling frequency
S
2
S clock generator architecture
8-bit Linear
Divider +
reshaping stage
MCKOE ODD I2SDIV[7:0]
presents the communication clock architecture. To achieve high-quality audio
provides example precision values for different clock configurations.
Doc ID 018909 Rev 4
if the packet length is 32-bit wide.
S
16-bit or 32-bit Right channel
32-bits or 64-bits
F
S
Divider by 4
I2SMOD
sampling point
0
0
Div2
1
1
MCKOE
CHLEN
RM0090
MCK
CK