ST STM32F40 Series Reference Manual page 687

Controller area network (bxCAN)
Bit 2 ERRI
Bit 1 SLAK
Note: The process of leaving Sleep mode is triggered when the SLEEP bit in the CAN_MCR
Bit 0 INAK
CAN transmit status register (CAN_TSR)
Address offset: 0x08
Reset value: 0x1C00 0000
31 30 29
LOW2 LOW1 LOW0 TME2
r r r
15 14 13
ABRQ
Reserved
1
Res.
rs
Bit 31 LOW2
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 2 has the lowest priority.
Bit 30 LOW1
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 1 has the lowest priority.
Bit 29 LOW0
This bit is set by hardware when more than one mailbox are pending for transmission and
mailbox 0 has the lowest priority.
Note: The LOW[2:0] bits are set to zero when only one mailbox is pending.
687/1422
:
Error interrupt
This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and
the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status
change interrupt if the ERRIE bit in the CAN_IER register is set.
This bit is cleared by software.
:
Sleep acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in
Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP
bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left Sleep mode (to be
synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
register is cleared. Please refer to the AWUM bit of the CAN_MCR register description
for detailed information for clearing SLEEP bit
:
Initialization acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is now in
initialization mode. This bit acknowledges the initialization request from the software (set
INRQ bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left the initialization mode (to
be synchronized on the CAN bus). To be synchronized the hardware has to monitor a
sequence of 11 consecutive recessive bits on the CAN RX signal.
28 27 26 25
TME1 TME0 CODE[1:0]
r r r r
12 11 10 9
TERR TXOK
ALST1
1 1
rc_w1 rc_w1 rc_w1
:
Lowest priority flag for mailbox 2
:
Lowest priority flag for mailbox 1
:
Lowest priority flag for mailbox 0
Doc ID 018909 Rev 4
24 23 22 21
ABRQ
2
Reserved
r rs
8 7 6 5
RQCP ABRQ
1 0
Reserved
rc_w1 rs
20 19 18 17
TERR TXOK
ALST2
2 2
rc_w1 rc_w1 rc_w1
4 3 2 1
TERR TXOK
ALST0
0 0
rc_w1 rc_w1 rc_w1
RM0090
16
RQCP
2
rc_w1
0
RQCP
0
rc_w1