Dma Stream X Number Of Data Register (Dma_Sxndtr) (X = 0; Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0 - ST STM32F40 Series Reference Manual

RM0090
Bits 0 EN: Stream enable / flag stream ready when read low
This bit is set and cleared by software.
0: Stream disabled
1: Stream enabled
This bit may be cleared by hardware:
When this bit is read as 0, the software is allowed to program the Configuration and FIFO
bits registers. It is forbidden to write these registers when the EN bit is read as 1.
Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the
9.5.6

DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)

Address offset: 0x14 + 0x18 × stream number
Reset value: 0x0000 0000
31 30 29
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data items to transfer
Number of data items to be transferred (0 up to 65535). This register can be written only
when the stream is disabled. When the stream is enabled, this register is read-only,
indicating the remaining data items to be transmitted. This register decrements after each
DMA transfer.
Once the transfer has completed, this register can either stay at zero (when the stream is in
normal mode) or be reloaded automatically with the previously programmed value in the
following cases:
If the value of this register is zero, no transaction can be served even if the stream is
enabled.
9.5.7

DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)

Address offset: 0x18 + 0x18 × stream number
Reset value: 0x0000 0000
31 30 29
rw rw rw
– on a DMA end of transfer (stream ready to be configured)
– if a transfer error occurs on the AHB master buses
– when the FIFO threshold on memory AHB port is not compatible with the size of the
burst
stream in DMA_LISR or DMA_HISR register must be cleared.
28 27 26 25
12 11 10 9
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– when the stream is configured in Circular mode.
– when the stream is enabled again by setting EN bit to '1'
28 27 26 25
rw rw rw rw
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
NDT[15:0]
rw rw rw rw
24 23 22 21
PAR[31:16]
rw rw rw rw
DMA controller (DMA)
20 19 18 17
4 3 2 1
rw rw rw rw
20 19 18 17
rw rw rw rw
16
0
rw
16
rw
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