Dma Interrupts; Dma Registers; Dma Low Interrupt Status Register (Dma_Lisr); Table 43. Dma Interrupt Requests - ST STM32F40 Series Reference Manual

DMA controller (DMA)
9.4

DMA interrupts

For each DMA stream, an interrupt can be produced on the following events:
●
Half-transfer reached
●
Transfer complete
●
Transfer error
●
Fifo error (overrun, underrun or FIFO level error)
●
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in
Table 43.
Half-transfer
Transfer complete
Transfer error
FIFO overrun/underrun
Direct mode error
Note: Before setting an Enable control bit to '1', the corresponding event flag should be cleared,
otherwise an interrupt is immediately generated.
9.5

DMA registers

The DMA registers can be accessed by words (32 bits).
9.5.1

DMA low interrupt status register (DMA_LISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
Reserved
r r r r
15 14 13 12
Reserved
r r r r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)
235/1422
DMA interrupt requests
Interrupt event
27 26 25
TCIF3 HTIF3 TEIF3
r r r
11 10 9
TCIF1 HTIF1 TEIF1
r r r
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
Doc ID 018909 Rev 4
Event flag
HTIF
TCIF
TEIF
FEIF
DMEIF
24 23 22
DMEIF3 Reserv FEIF3 TCIF2
ed
r r
8 7 6
DMEIF1 Reserv FEIF1 TCIF0
ed
r r
Enable control bit
DMEIE
21 20 19 18
HTIF2 TEIF2 DMEIF2 Reserv
r r r r
5 4 3 2
HTIF0 TEIF0 DMEIF0 Reserv
r r r r
RM0090
Table 43.
HTIE
TCIE
TEIE
FEIE
17 16
FEIF2
ed
r
1 0
FEIF0
ed
r