Sdio Data Timer Register (Sdio_Dtimer); Sdio Data Length Register (Sdio_Dlen) - ST STM32F40 Series Reference Manual

RM0090
28.9.7

SDIO data timer register (SDIO_DTIMER)

Address offset: 0x24
Reset value: 0x0000 0000
The SDIO_DTIMER register contains the data timeout period, in card bus clock periods.
A counter loads the value from the SDIO_DTIMER register, and starts decrementing when
the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0
while the DPSM is in either of these states, the timeout status flag is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:0 DATATIME: Data timeout period
Data timeout period expressed in card bus clock periods.
Note: A data transfer must be written to the data timer register and the data length register before
being written to the data control register.
28.9.8

SDIO data length register (SDIO_DLEN)

Address offset: 0x28
Reset value: 0x0000 0000
The SDIO_DLEN register contains the number of data bytes to be transferred. The value is
loaded into the data counter when data transfer starts.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:25 Reserved, must be kept at reset value
Bits 24:0 DATALENGTH: Data length value
Number of data bytes to be transferred.
Note: For a block data transfer, the value in the data length register must be a multiple of the block
size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the
data length register before being written to the data control register.
For an SDIO multibyte transfer the value in the data length register must be between 1 and
512.
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Doc ID 018909 Rev 4
Secure digital input/output interface (SDIO)
DATATIME
DATALENGTH
9 8 7 6 5 4 3
9 8 7 6 5 4 3
2 1 0
2 1 0
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