Inter-Integrated Circuit (I 2 C) Interface; I 2 C Introduction; I 2 C Main Features - ST STM32F40 Series Reference Manual

RM0090
25 Inter-integrated circuit (I
This section applies to the whole STM32F4xx family, unless otherwise specified.
2
25.1 I C introduction
2
I C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller
and the serial I
sequencing, protocol, arbitration and timing. It supports standard and fast speed modes. It is
also SMBus 2.0 compatible.
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(system management bus) and PMBus (power management bus).
Depending on specific device implementation DMA capability can be available for reduced
CPU overload.
2
25.2 I C main features
●
Parallel-bus/I
●
Multimaster capability: the same interface can act as Master or Slave
2
●
I C Master features:
–
–
2
●
I C Slave features:
–
–
–
●
Generation and detection of 7-bit/10-bit addressing and General Call
●
Supports different communication speeds:
–
–
●
Programmable digital noise filter for STM32F42xxx and STM32F43xxx
●
Status flags:
–
–
–
●
Error flags:
–
–
–
–
●
2 Interrupt vectors:
–
2
C bus. It provides multimaster capability, and controls all I
2
C protocol converter
Clock generation
Start and Stop generation
2
Programmable I C Address detection
Dual Addressing Capability to acknowledge 2 slave addresses
Stop bit detection
Standard Speed (up to 100 kHz)
Fast Speed (up to 400 kHz)
Transmitter/Receiver mode flag
End-of-Byte transmission flag
2
I C busy flag
Arbitration lost condition for master mode
Acknowledgement failure after address/ data transmission
Detection of misplaced start or stop condition
Overrun/Underrun if clock stretching is disabled
1 Interrupt for successful address/ data communication
Doc ID 018909 Rev 4
Inter-integrated circuit (I
2
C) interface
2
C) interface
2
C bus-specific
708/1422