I 2 S Interrupts; Dma Features; Table 126. I - ST STM32F40 Series Reference Manual

RM0090
change. If the synchronization is lost, to recover from this state and resynchronize the
external master device with the I2S slave device, follow the steps below:
1. Disable the I2S
2. Re-enable it when the correct level is detected on the WS line (WS line is high in I2S
mode, or low for MSB- or LSB-justified or PCM modes).
Desynchronization between the master and slave device may be due to noisy environment
on the SCK communication clock or on the WS frame synchronization line. An error interrupt
can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
2
27.4.9 I S interrupts
Table 126

Table 126. I

Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
Frame error flag
27.4.10

DMA features

DMA is working in exactly the same way as for the SPI mode. There is no difference on the
2
I S. Only the CRC feature is not available in I
protection system.
2
provides the list of I S interrupts.
2
S interrupt requests
Interrupt event
Doc ID 018909 Rev 4
Serial peripheral interface (SPI)
Event flag
TXE
RXNE
OVR
UDR
FRE
2
S mode since there is no data transfer
Enable Control bit
TXEIE
RXNEIE
ERRIE
ERRIE
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