RM0090
sector cannot be erased or programmed. Consequently, a mass erase cannot be performed
if one of the sectors is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted
(sector protected by write protection bit, OTP part locked or part of the Flash memory that
can never be written like the ICP), the write protection error flag (WRPERR) is set in the
FLASH_SR register.
Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Write protection error flag
If an erase/program operation to a write protected area of the Flash memory is performed,
the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
If an erase operation is requested, the WRPERR bit is set when:
●
Mass, bank, sector erase are configured (MER or MER/MER1 and SER = 1)
●
A sector erase is requested and the Sector Number SNB field is not valid
●
A mass erase is requested while at least one of the user sector is write protected by
option bit (MER or MER/MER1 = 1 and nWRPi = 0 with 0 ≤ i ≤ 11 bits in the
FLASH_OPTCRx register
●
A sector erase is requested on a write protected sector. (SER = 1, SNB = i and
nWRPi = 0 with 0 ≤ i ≤ 11 bits in the FLASH_OPTCRx register)
●
The Flash memory is readout protected and an intrusion is detected.
If a program operation is requested, the WRPERR bit is set when:
●
A write operation is performed on system memory or on the reserved part of the user
specific sector.
●
A write operation is performed to the user configuration sector
●
A write operation is performed on a sector write protected by option bit.
●
A write operation is requested on an OTP area which is already locked
●
The Flash memory is read protected and an intrusion is detected.
3.7
One-time programmable bytes
Table 14
Table 14.
Block
0
1
.
.
.
shows the organization of the one-time programmable (OTP) part of the OTP area.
OTP area organization
[128:96]
OTP0
OTP0
OTP1
OTP1
Doc ID 018909 Rev 4
[95:64]
[63:32]
OTP0
OTP0
OTP0
OTP0
OTP1
OTP1
OTP1
OTP1
.
.
.
Embedded Flash memory interface
[31:0]
Address byte 0
OTP0
OTP0
OTP1
OTP1
0x1FFF 7800
0x1FFF 7810
0x1FFF 7820
0x1FFF 7830
.
.
.
74/1422
Need help?
Do you have a question about the STM32F40 Series and is the answer not in the manual?
Questions and answers