Cryp Registers; Cryp Control Register (Cryp_Cr) For; Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F40 Series Reference Manual

RM0090
Each request signal remains asserted until the relevant DMA clear signal is asserted. After
the request clear signal is deasserted, a request signal can become active again, depending
on the above described conditions. All request signals are deasserted if the CRYP
peripheral is disabled or the DMA enable bit is cleared (DIEN bit for the IN FIFO and DOEN
bit for the OUT FIFO in the CRYP_DMACR register).
Note: The DMA controller must be configured to perform burst of 4 words or less. Otherwise some
data could be lost.
In order to let the DMA controller empty the OUT FIFO before filling up the IN FIFO, the
OUTDMA channel should have a higher priority than the INDMA channel.
20.6

CRYP registers

The cryptographic core is associated with several control and status registers, eight key
registers and four initialization vectors registers.
20.6.1

CRYP control register (CRYP_CR) for

STM32F405xx/07xx and STM32F415xx/17xx

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
CRYPEN FFLUSH
rw w
Bit 31:18 Reserved, must be kept at reset value
Bit 17:16 Reserved, must be kept at reset value
Bits 13:10 Reserved, must be kept at reset value
28 27 26 25
12 11 10 9
KEYSIZE
Reserved
rw
Bit 15 CRYPEN: Cryptographic processor enable
0: CRYP processor is disabled
1: CRYP processor is enabled
Note: The CRYPEN bit is automatically cleared by hardware when the key
preparation process ends (ALGOMODE=111b) or GCM_CCM init Phase
Bit 14 FFLUSH: FIFO flush
When CRYPEN = 0, writing this bit to 1 flushes the IN and OUT FIFOs (that is
read and write pointers of the FIFOs are reset. Writing this bit to 0 has no effect.
When CRYPEN = 1, writing this bit to 0 or 1 has no effect.
Reading this bit always returns 0.
Doc ID 018909 Rev 4
Cryptographic processor (CRYP)
24 23 22 21
Reserved
8 7 6 5
DATATYPE ALGOMODE[2:0]
rw rw rw rw
20 19 18 17
4 3 2 1
ALGODIR Res.
rw rw rw
16
0
Res.
576/1422