Timx Slave Mode Control Register (Timx_Smcr) - ST STM32F40 Series Reference Manual

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TIMx slave mode control register (TIMx_SMCR)

Address offset: 0x08

Reset value: 0x0000

Bit 15 ETP: External trigger polarity

Bit 14 ECE: External clock enable

Bits 13:12 ETPS: External trigger prescaler

Bits 11:8 ETF[3:0]: External trigger filter

This bit selects whether ETR or ETR is used for trigger operations

0: ETR is noninverted, active at high level or rising edge

1: ETR is inverted, active at low level or falling edge

This bit enables External clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF

1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI

connected to ETRF (SMS=111 and TS=111).

2: It is possible to simultaneously use external clock mode 2 with the following slave modes:

reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to

ETRF in this case (TS bits must not be 111).

3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the

external clock input is ETRF.

External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A

prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

This bit-field then defines the frequency used to sample ETRP signal and the length of the

digital filter applied to ETRP. The digital filter is made of an event counter in which N events

are needed to validate a transition on the output:

0000: No filter, sampling is done at f

Doc ID 018909 Rev 4

General-purpose timers (TIM2 to TIM5)

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