Figure 352. Receive Dma Operation - ST STM32F40 Series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
frame (for example, because the receive FIFO was full before the time stamp could be
written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time
stamping is not enabled), RDES2 and RDES3 remain unchanged.

Figure 352. Receive DMA operation

Set descriptor error
959/1422
RxDMA suspended
Frame transfer
complete?
Yes Flush disabled ?
Flush the
remaining frame
Flush Own bit set
No
for next desc?
disabled ?
No
Yes Yes
Close RDES0 as
intermediate descriptor
Doc ID 018909 Rev 4
Start RxDMA
(Re-)Fetch next
Poll demand /
descriptor
new frame available
(AHB)
error?
No
Yes
No Own bit set?
Yes
No
Frame data
available ?
Yes
No
Write data to buffer(s)
(AHB)
error?
No
Fetch next descriptor
(AHB)
error?
No
Frame transfer
No
complete?
Yes
Time stamp
present?
No
Close RDES0 as last
descriptor
(AHB)
error?
Yes
Start Stop RxDMA
Yes
No
Wait for frame data
Yes
Yes
Write time stamp to
Yes
RDES2 & RDES3
(AHB)
No Yes
error?
No
RM0090
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