ST STM32F40 Series Reference Manual page 978

RM0090
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:11 PA: PHY address
Bits 10:6 MR: MII register
Bit 5 Reserved, must be kept at reset value.
Bits 4:2 CR: Clock range
Bit 1 MW: MII write
Bit 0 MB: MII busy
Ethernet MAC MII data register (ETH_MACMIIDR)
Address offset: 0x0014
Reset value: 0x0000 0000
The MAC MII Data register stores write data to be written to the PHY register located at the
address specified in ETH_MACMIIAR. ETH_MACMIIDR also stores read data from the PHY
register located at the address specified by ETH_MACMIIAR.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MD: MII data
This contains the 16-bit data value read from the PHY after a Management Read operation,
or the 16-bit data value to be written to the PHY before a Management Write operation.
Ethernet (ETH): media access control (MAC) with DMA controller
This field tells which of the 32 possible PHY devices are being accessed.
These bits select the desired MII register in the selected PHY device.
The CR clock range selection determines the HCLK frequency and is used to decide the
frequency of the MDC clock:
Selection HCLK
000 60-100 MHz
001 100-150 MHz HCLK/62
010 20-35 MHz
011 35-60 MHz
100 150-168 MHz HCLK/102
101, 110, 111 Reserved
When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If
this bit is not set, this will be a Read operation, placing the data in the MII Data register.
This bit should read a logic 0 before writing to ETH_MACMIIAR and ETH_MACMIIDR. This bit
must also be reset to 0 during a Write to ETH_MACMIIAR. During a PHY register access, this
bit is set to 0b1 by the application to indicate that a read or write access is in progress.
ETH_MACMIIDR (MII Data) should be kept valid until this bit is cleared by the MAC during a
PHY Write operation. The ETH_MACMIIDR is invalid until this bit is cleared by the MAC
during a PHY Read operation. The ETH_MACMIIAR (MII Address) should not be written to
until this bit is cleared.
Reserved
Doc ID 018909 Rev 4
MDC Clock
HCLK/42
HCLK/16
HCLK/26
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