Timx Capture/Compare Register 3 (Timx_Ccr3); Timx Capture/Compare Register 4 (Timx_Ccr4) - ST STM32F40 Series Reference Manual

RM0090
15.4.15

TIMx capture/compare register 3 (TIMx_CCR3)

Address offset: 0x3C
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
15.4.16

TIMx capture/compare register 4 (TIMx_CCR4)

Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5).
Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1.
2.
28 27 26 25
CCR3[31:16] (depending on timers)
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12 11 10 9
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If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).
28 27 26 25
CCR4[31:16] (depending on timers)
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12 11 10 9
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if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
Doc ID 018909 Rev 4
General-purpose timers (TIM2 to TIM5)
24 23 22 21
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8 7 6 5
CCR3[15:0]
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24 23 22 21
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8 7 6 5
CCR4[15:0]
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20 19 18 17
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4 3 2 1
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20 19 18 17
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4 3 2 1
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16
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0
rw
16
rw
0
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476/1422