Figure 34. Single Adc Block Diagram - ST STM32F40 Series Reference Manual

Analog-to-digital converter (ADC)

Figure 34. Single ADC block diagram

V REF+
V REF-
V DDA
V SSA
ADCx_IN0
ADCx_IN1
GPIO
ports
ADCx_IN15
Temp. sensor
V REFINT
V BAT
TIM1_CH4
TIM1_TRGO
TIM2_CH1
TIM2_TRGO
TIM3_CH2
TIM3_CH4
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_TRGO
TIM5_CH4
TIM5_TRGO
TIM8_CH2
TIM8_CH3
TIM8_CH4
EXTI_15
EXTI_11
265/1422
DMA overrun
End of conversion
End of injected conversion
Analog watchdog event
Analog
mux
up to 4
Injected
channels
up to 16
JEXTSEL[3:0] bits
JEXTEN
[1:0] bits
Start trigger
(injected group)
Doc ID 018909 Rev 4
Interrupt
Flags
enable bits
OVR OVRIE
EOC EOCIE
JEOC JEOCIE
AWD AWDIE
Analog watchdog
Compare result
Higher threshold (12 bits)
Lower threshold (12 bits)
Injected data registers
(4 x 16 bits)
Regular data register
(16 bits)
Analog to digital
converter
Regular
channels
EXTSEL[3:0] bits
EXTEN
[1:0] bits
Start trigger
(regular group)
RM0090
ADC Interrupt to NVIC
DMA request
ADCCLK
From ADC prescaler
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM2_CH3
TIM2_CH4
TIM2_TRGO
TIM3_CH1
TIM3_TRGO
TIM4_CH4
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM8_CH1
TIM8_TRGO
ai16046