Figure 31. Fifo Structure - ST STM32F40 Series Reference Manual

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The structure of the FIFO differs depending on the source and destination data widths, and

is described in

Figure 31. FIFO structure

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

FIFO threshold and burst configuration

Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR

content pointed by the FIFO threshold must exactly match to an integer number of memory

burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or

DMA_LISR register) will be generated when the stream is enabled, then the stream will be

automatically disabled. The allowed and forbidden configurations are described in the

Table 41: FIFO threshold

Figure 31: FIFO

Source: byte

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

configurations.

FIFO threshold configurations

FIFO level MBURST = INCR4

1 burst of 4 beats

2 bursts of 4 beats

3 bursts of 4 beats

4 bursts of 4 beats

Doc ID 018909 Rev 4

MBURST = INCR8

1 burst of 8 beats

2 bursts of 8 beats

DMA controller (DMA)

Destination: word

W3, W2, W1, W0

Destination: half-word

H7, H6, H5, H4, H3, H2, H1, H0

Destination: word

W3, W2, W1, W0

Destination: byte

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

MBURST = INCR16

1 burst of 16 beats

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Figure 31. Fifo Structure - ST STM32F40 Series Reference Manual

Figure 31. FIFO structure

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