Rtc Functional Description; Clock And Prescalers; Figure 222. Rtc Block Diagram - ST STM32F40 Series Reference Manual

Real-time clock (RTC)

Figure 222. RTC block diagram

RTCCLK
LSE (32.768 Hz)
Smooth
HSE_RTC
calibration
(4 MHz max)
RTC_CALR
LSI
RTC_TAMP1
1. On STM32F4xx devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, respectively.
23.3

RTC functional description

23.3.1

Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see
●
A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
● A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
627/1422
512 Hz
ck_apre
(default 256 Hz)
RTC_PRER RTC_PRER
Coarse
Calibration
Syn chronous
Asyn ch.
RTC_CALIBR
15-bit prescaler
7-bit prescaler
(default = 256)
(default = 128)
Shadow register
(RTC_SSR)
WUCKSEL[1:0]
Prescaler
RTC_WUTR
/ 2, 4, 8, 16
16-bit wakeup
auto-reload timer
Section 6: Reset and clock control for
Figure 222: RTC block
Doc ID 018909 Rev 4
RTC_TS
1 Hz
Alarm A
(RTC_ALRMAR
RTC_ALRMASSR
ck spre
registers)
(default 1 Hz)
Calendar
Shadow registers
(RTC_TR,
RTC_DR)
Alarm B
(RTC_ALRMBR
RTC_ALRMBSSR
registers)
Backup and
RTC tamper
control registers
RTC_TAMP2
diagram):
Time stamp
TSF
registe rs
RTC_CALIB
Output
control
ALRAF
=
RTC_ALARM
ALRBF
= =
WUTF
TAMPE
TSE
(RCC).
RM0090
RTC_OUT
RTC_AF1
RTC_AF2
MS19902V3