Regular Simultaneous Mode; Figure 42. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode; Figure 43. Injected Simultaneous Mode On 4 Channels: Triple Adc Mode - ST STM32F40 Series Reference Manual

Analog-to-digital converter (ADC)

Figure 42. Injected simultaneous mode on 4 channels: dual ADC mode

ADC1
ADC2
Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
●
The converted data are stored into the ADC_JDRx registers of each ADC interface.
●
A JEOC interrupt is generated (if enabled on one of the three ADC interfaces) when the
ADC1/ADC2/ADC3's injected channels have all been converted.

Figure 43. Injected simultaneous mode on 4 channels: triple ADC mode

ADC1
ADC2
ADC3
11.9.2

Regular simultaneous mode

This mode is performed on a regular group of channels. The external trigger source comes
from the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the
ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.
Note: Do not convert the same channel on the two/three ADCs (no overlapping sampling times for
the two/three ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the long conversion time of the 2 sequences
(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest
sequence may restart while the ADC with the longest sequence is completing the previous
conversions.
Injected conversions must be disabled.
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CH0 CH1
CH15 CH14
Trigger
Sampling
Conversion
CH0 CH1
CH15 CH14
CH10 CH12
Trigger
Sampling
Conversion
Doc ID 018909 Rev 4
...
CH2 CH3
...
CH13 CH12
End of conversion on ADC1 and ADC2
...
CH2 CH3
...
CH13 CH12
...
CH8 CH5
End of conversion on ADC1, ADC2 and ADC3
CH15
CH0
ai16054
CH15
CH0
CH2
ai16055
RM0090