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RM0430
Reference manual
®
STM32F413/423 advanced ARM
-based 32-bit MCUs
This reference manual targets application developers. It provides complete information on
how to use the memory and the peripherals of the STM32F413/423 microcontrollers.
The STM32F413/423 is a line of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics refer to the
datasheet.
®
®
®
For information on the ARM
Cortex
-M4 with FPU core, refer to the Cortex
-M4 with FPU
Technical Reference Manual.
Related documents
Available from STMicroelectronics web site www.st.com:
• STM32F413/423xG/xH datasheet
®
• PM0214 "STM32F3 and STM32F4 Series Cortex
-M4 with FPU-M4 programming
®
®
manual" for information on the ARM
Cortex
-M4 with FPU.
March 2017
DocID029473 Rev 3
1/1284
www.st.com
1
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Summary of Contents for ST STM32F413
- Page 1 This reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F413/423 microcontrollers. The STM32F413/423 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics refer to the datasheet.
-
Page 2: Table Of Contents
Contents RM0430 Contents Documentation conventions ....... . . 51 List of abbreviations for registers ....... 51 Glossary . -
Page 3: Table Of Contents
RM0430 Contents 3.5.4 Programming ..........71 3.5.5 Interrupts . -
Page 4: Table Of Contents
PWR register map ......... .114 Reset and clock control (RCC) for STM32F413/423 ....115 Reset . -
Page 5: Table Of Contents
RM0430 Contents 6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..136 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F413xx ........138 6.3.7 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F423xx . -
Page 6: Table Of Contents
Contents RM0430 GPIO main features ........181 GPIO functional description . -
Page 7: Table Of Contents
RM0430 Contents SYSCFG registers ......... 201 8.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . -
Page 8: Table Of Contents
Contents RM0430 9.3.18 Stream configuration procedure ......229 9.3.19 Error management ........230 DMA interrupts . -
Page 9: Table Of Contents
RM0430 Contents 11.1 FSMC main features ........261 11.2 Block diagram . -
Page 10: Table Of Contents
Contents RM0430 12.5.1 QUADSPI control register (QUADSPI_CR) ..... 320 12.5.2 QUADSPI device configuration register (QUADSPI_DCR) ..323 12.5.3 QUADSPI status register (QUADSPI_SR) . -
Page 11: Table Of Contents
RM0430 Contents 13.8.3 Conversions without DMA and without overrun detection ..343 13.9 Temperature sensor ........343 13.10 Battery charge monitoring . -
Page 12: Table Of Contents
Contents RM0430 14.4 Dual DAC channel conversion ....... . 366 14.4.1 Independent trigger without wave generation . -
Page 13: Table Of Contents
RM0430 Contents 15.1 Introduction ..........381 15.2 DFSDM main features . -
Page 14: Table Of Contents
Contents RM0430 15.8.3 DFSDM interrupt and status register (DFSDM_FLTxISR) ..423 15.8.4 DFSDM interrupt flag clear register (DFSDM_FLTxICR) ... 425 15.8.5 DFSDM injected channel group selection register (DFSDM_FLTxJCHGR) . -
Page 15: Table Of Contents
RM0430 Contents 16.7.2 Validation conditions ........448 16.7.3 Data collection . -
Page 16: Table Of Contents
Contents RM0430 17.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) ..502 17.4.5 TIM1&TIM8 status register (TIMx_SR) ......504 17.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . -
Page 17: Table Of Contents
RM0430 Contents 18.3.15 Timer synchronization ........556 18.3.16 Debug mode . -
Page 18: Table Of Contents
Contents RM0430 19.3.7 Forced output mode ........598 19.3.8 Output compare mode . -
Page 19: Table Of Contents
RM0430 Contents Basic timers (TIM6/7) ........631 20.1 Introduction . -
Page 20: Table Of Contents
Contents RM0430 21.4.13 Encoder mode ......... . . 653 21.5 LPTIM interrupts . -
Page 21: Table Of Contents
RM0430 Contents 23.6.2 Configuration register (WWDG_CFR) ......678 23.6.3 Status register (WWDG_SR) ....... . 678 23.6.4 WWDG register map . -
Page 22: Table Of Contents
Contents RM0430 24.14.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) ..710 24.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) ..711 24.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) . 711 24.14.13 AES key register 4 (AES_KEYR4) (key[159:128]) . -
Page 23: Table Of Contents
RM0430 Contents 25.6.5 RTC prescaler register (RTC_PRER) ......738 25.6.6 RTC wakeup timer register (RTC_WUTR) ..... . 739 25.6.7 RTC calibration register (RTC_CALIBR) . -
Page 24: Table Of Contents
Contents RM0430 26.4.14 Error conditions ......... . 798 26.4.15 DMA requests . -
Page 25: Table Of Contents
RM0430 Contents 27.6.2 C Control register 2 (I2C_CR2) ......843 27.6.3 C Own address register 1 (I2C_OAR1) ..... . . 845 27.6.4 C Own address register 2 (I2C_OAR2) . -
Page 26: Table Of Contents
Contents RM0430 28.6.5 Control register 2 (USART_CR2) ......902 28.6.6 Control register 3 (USART_CR3) ......903 28.6.7 Guard time and prescaler register (USART_GTPR) . -
Page 27: Table Of Contents
RM0430 Contents 29.6.7 S error flags ..........942 29.6.8 S interrupts . -
Page 28: Table Of Contents
Contents RM0430 30.12.3 Companding mode ........969 30.12.4 Output data line management on an inactive slot . -
Page 29: Table Of Contents
RM0430 Contents 31.4.7 Stream access, stream write and stream read (MultiMediaCard only) ........1012 31.4.8 Erase: group erase and sector erase . -
Page 30: Table Of Contents
Contents RM0430 31.8.13 SDIO mask register (SDIO_MASK) ......1045 31.8.14 SDIO FIFO counter register (SDIO_FIFOCNT) ....1047 31.8.15 SDIO data FIFO register (SDIO_FIFO) . -
Page 31: Table Of Contents
RM0430 Contents 32.9.5 bxCAN register map ........1092 USB on-the-go full-speed (OTG_FS) . -
Page 32: Table Of Contents
Contents RM0430 33.12 OTG_FS system performance ....... . 1118 33.13 OTG_FS interrupts ......... 1118 33.14 OTG_FS control and status registers . -
Page 33: Table Of Contents
RM0430 Contents 33.15.25 OTG Host channel-x characteristics register (OTG_HCCHARx) (x = 0..11, where x = Channel_number) ..... . 1159 33.15.26 OTG Host channel-x interrupt register (OTG_HCINTx) (x = 0..11, where x = Channel_number) . -
Page 34: Table Of Contents
Contents RM0430 33.15.49 OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) (x = 0..5, where x = Endpoint_number) ........1185 33.15.50 OTG device OUT endpoint-x transfer size register (OTG_DOEPTSIZx) (x = 1..5, where x = Endpoint_number) . -
Page 35: Table Of Contents
RM0430 Contents 34.8.3 SW-DP state machine (reset, idle states, ID code) ....1257 34.8.4 DP and AP read/write accesses ......1257 34.8.5 SW-DP registers . -
Page 36: Table Of Contents
Contents RM0430 Device electronic signature ....... . 1276 35.1 Unique device ID register (96 bits) ......1276 35.2 Flash size . -
Page 37: Table Of Contents
PWR - register map and reset values ........114 Table 24. RCC register map and reset values for STM32F413/423......178 Table 25. -
Page 38: Table Of Contents
List of tables RM0430 Table 49. NOR Flash/PSRAM: example of supported memories and transactions ... . . 269 Table 50. FSMC_BCRx bit fields ........... 272 Table 51. -
Page 39: Table Of Contents
Table 127. STM32F413/423 FMPI2C implementation ........ -
Page 40: Table Of Contents
List of tables RM0430 oversampling by 8............871 Table 147. -
Page 41: Table Of Contents
Table 199. STM32F413/423 CAN implementation ........ -
Page 42: Table Of Contents
Basic structure of a five-volt tolerant I/O port bit ....... . 182 Figure 18. Selecting an alternate function on STM32F413/423 ......186 Figure 19. -
Page 43: Table Of Contents
RM0430 List of figures Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) ... 290 Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)....292 Figure 51. -
Page 44: Table Of Contents
List of figures RM0430 Figure 99. Counter timing diagram, internal clock divided by N......461 Figure 100. -
Page 45: Table Of Contents
RM0430 List of figures Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 ....534 Figure 152. Counter timing diagram, internal clock divided by N......534 Figure 153. -
Page 46: Table Of Contents
List of figures RM0430 Figure 201. Control circuit in reset mode ..........604 Figure 202. -
Page 47: Table Of Contents
RM0430 List of figures Figure 250. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=1 ..770 Figure 251. Transfer bus diagrams for FMPI2C slave transmitter ......771 Figure 252. -
Page 48: Table Of Contents
List of figures RM0430 Figure 302. RTS flow control ............894 Figure 303. -
Page 49: Table Of Contents
RM0430 List of figures Figure 351. (Multiple) block read operation ..........994 Figure 352. -
Page 50: Table Of Contents
List of figures RM0430 Figure 403. A-device HNP ............1242 Figure 404. -
Page 51: Documentation Conventions
RM0430 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit. Reading this bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. -
Page 52: System And Memory Overview
System and memory overview RM0430 System and memory overview System architecture In STM32F413/423, the main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Six masters: ® – Cortex -M4 with FPU core I-bus, D-bus and S-bus –... -
Page 53: I-Bus
RM0430 System and memory overview Figure 1. System architecture 2.1.1 I-bus ® This bus connects the Instruction bus of the Cortex -M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory/SRAM1/SRAM2). -
Page 54: Dma Peripheral Bus
System and memory overview RM0430 2.1.5 DMA peripheral bus This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: Flash memory and internal SRAM1/SRAM2. -
Page 55: Memory Organization
RM0430 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. -
Page 56: Memory Map And Register Boundary Addresses
RM0430 All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to Memory map and register boundary addresses and peripheral sections. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map. - Page 57 RM0430 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4002 6800 - 0x4FFF FFFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 4000 - 0X4002 5FFF Reserved 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF 0x4002 3400 - 0x4002 37FF Reserved...
- Page 58 RM0430 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4001 6800 - 0x4001 FFFF Reserved 0x4001 6400 - 0x4001 67FF DFSDM2 0x4001 6000 - 0x4001 63FF DFSDM1 0x4001 5C00 - 0x4001 5FFF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF...
- Page 59 RM0430 Table 1. Register boundary addresses (continued) Boundary address Peripheral 0x4000 8000 - 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF CAN3 0x4000 6800 - 0x4000 6BFF CAN2...
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Page 60: Embedded Sram
RM0430 Embedded SRAM STM32F413/423 devices feature 320 Kbytes of system SRAM. The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). Read and write operations are performed at CPU speed with 0 wait state. -
Page 61: Boot Configuration
RM0430 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit –... -
Page 62: Table 3. Embedded Bootloader Interfaces
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to 26 MHz). The embedded bootloader code is located in system memory. It is programmed by ST during production. For additional information, refer to application note AN2606. -
Page 63: Table 4. Memory Mapping Vs. Boot Mode/Physical Remap In Stm32F413/423
RM0430 Table 4. Memory mapping vs. Boot mode/physical remap in STM32F413/423 Boot/Remap in main Boot/Remap in Boot/Remap in Addresses Flash memory embedded SRAM System memory 0x2000 0000 - 0x2003 FFFF SRAM (256 KB) SRAM (256KB) SRAM (256KB) 0x1FFF 0000 - 0x1FFF 77FF... -
Page 64: Embedded Flash Memory Interface
Embedded Flash memory interface RM0430 Embedded Flash memory interface Introduction The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines. -
Page 65: Embedded Flash Memory
RM0430 Embedded Flash memory interface Embedded Flash memory The Flash memory has the following main features: • Capacity up to 1.5 Mbyte • 128 bits wide data read • Byte, half-word, word and double word write • Sector and mass erase •... -
Page 66: Read Interface
Embedded Flash memory interface RM0430 Table 5. Flash module organization (continued) Block Name Block base addresses Size OTP area 0x1FFF 7800 - 0x1FFF 7A0F 528 byte Option bytes 0x1FFF C000 - 0x1FFF C00F 16 byte Read interface 3.4.1 Relation between CPU clock frequency and Flash memory read time To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. -
Page 67: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
RM0430 Embedded Flash memory interface Increasing the CPU frequency Program the new number of wait states to the LATENCY bits in the FLASH_ACR register Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR... -
Page 68: Figure 4. Sequential 32-Bit Instruction Execution
Embedded Flash memory interface RM0430 Figure 4 shows the execution of sequential 32-bit instructions with and without prefetch when 3 WSs are needed to access the Flash memory. Figure 4. Sequential 32-bit instruction execution 68/1284 DocID029473 Rev 3... -
Page 69: Erase And Program Operations
RM0430 Embedded Flash memory interface When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states. Instruction cache memory To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction cache memory. -
Page 70: Program/Erase Parallelism
Embedded Flash memory interface RM0430 Note: The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall until the BSY bit is cleared. -
Page 71: Programming
RM0430 Embedded Flash memory interface Mass Erase To perform Mass Erase, the following sequence is recommended: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Set the MER bit in the FLASH_CR register Set the STRT bit in the FLASH_CR register Wait for the BSY bit to be cleared Note:... -
Page 72: Interrupts
Embedded Flash memory interface RM0430 Programming and caches If a Flash memory write access concerns some data in the data cache, the Flash write access modifies the data in the Flash memory and the data in the cache. If an erase operation in Flash memory also concerns data in the data or instruction cache, you have to make sure that these data are rewritten before they are accessed during code execution. -
Page 73: Table 10. Description Of The Option Bytes
RM0430 Embedded Flash memory interface Table 10. Description of the option bytes Option bytes (word, address 0x1FFF C000) RDP: Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0xAA: Level 0, no protection Bits 15:8 0xCC: Level 2, chip protection (debug and boot from RAM features disabled) Others: Level 1, read protection of memories (debug features limited) -
Page 74: Programming User Option Bytes
Embedded Flash memory interface RM0430 Table 10. Description of the option bytes nWRP15_14: Non Write Protection of sector 15 and 14 If SPRMOD is reset (default value): 0: Write protection active on sector 15 and 14. Bit 14 1: Write protection not active on sector 15 and 14. If SPRMOD is set (active): 0: PCROP protection not active on sector 15 and 14. - Page 75 RM0430 Embedded Flash memory interface Flash memory are possible in all boot configurations (Flash user boot, debug or boot from RAM). • Level 1: read protection enabled It is the default read protection level after option byte erase. The read protection Level 1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and Level 2, respectively) into the RDP option byte.
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Page 76: Write Protections
Embedded Flash memory interface RM0430 Table 11. Access versus read protection level Debug features, Boot from RAM or Booting from Flash memory Protection from System memory bootloader Memory area Level Read Write Erase Read Write Erase Level 1 Main Flash Memory Level 2 Level 1 Option Bytes... -
Page 77: Proprietary Code Readout Protection (Pcrop)
RM0430 Embedded Flash memory interface If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit, OTP part locked or part of the Flash memory that can never be written like the ICP), the write protection error flag (WRPERR) is set in the FLASH_SR register. -
Page 78: Figure 6. Pcrop Levels
Embedded Flash memory interface RM0430 Figure 6. PCROP levels The deactivation of the SPRMOD and/or the unprotection of PCROPed user sectors can only occur when, at the same time, the RDP level changes from 1 to 0. If this condition is not respected, the user option byte modification is canceled and the write error WRPERR flag is set. -
Page 79: One-Time Programmable Bytes
RM0430 Embedded Flash memory interface One-time programmable bytes Table 12 shows the organization of the one-time programmable (OTP) part of the OTP area. Table 12. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 OTP0 OTP0 OTP0 OTP0 0x1FFF 7800 OTP0 OTP0... -
Page 80: Flash Interface Registers
Embedded Flash memory interface RM0430 Flash interface registers 3.8.1 Flash access control register (FLASH_ACR) The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. -
Page 81: Flash Key Register (Flash_Keyr)
RM0430 Embedded Flash memory interface 3.8.2 Flash key register (FLASH_KEYR) The Flash key register is used to allow access to the Flash control register and so, to allow program and erase operations. Address offset: 0x04 Reset value: 0x0000 0000 Access: no wait state, word access KEY[31:16] KEY[15:0] Bits 31:0 FKEYR: FPEC key... -
Page 82: Flash Status Register (Flash_Sr)
Embedded Flash memory interface RM0430 3.8.4 Flash status register (FLASH_SR) The Flash status register gives information on ongoing program and erase operations. Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. -
Page 83: Flash Control Register (Flash_Cr)
RM0430 Embedded Flash memory interface Bits 3:2 Reserved, must be kept cleared. Bit 1 OPERR: Operation error Set by hardware when a flash operation (programming / erase /read) request is detected and can not be run because of parallelism, alignment, or write protection error. This bit is set only if error interrupts are enabled (ERRIE = 1). -
Page 84: Flash Option Control Register (Flash_Optcr)
Embedded Flash memory interface RM0430 Bits 9:8 PSIZE: Program size These bits select the program parallelism. 00 program x8 01 program x16 10 program x32 11 program x64 Bit 7 Reserved, must be kept cleared. Bits 6:3 SNB: Sector number These bits select the sector to erase. - Page 85 RM0430 Embedded Flash memory interface Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits 0: PCROP disabled, nWPRi bits used for Write Protection on sector i 1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i Bit 30 nWRP14_15: Not write protect This bit contains the value of the write-protection option byte of sectors 14 and 15.
- Page 86 Embedded Flash memory interface RM0430 Bits 3:2 BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V drops below the selected BOR level, a device reset is generated.
-
Page 87: Flash Interface Register Map
RM0430 Embedded Flash memory interface 3.8.7 Flash interface register map Table 13. Flash register map and reset values Offset Register FLASH_ACR LATENCY 0x00 Reset value FLASH_KEYR KEY[31:16] KEY[15:0] 0x04 Reset value 0 0 0 FLASH_ OPTKEYR[31:16] OPTKEYR[15:0] OPTKEYR 0x08 Reset value 0 0 0 FLASH_SR 0x0C... -
Page 88: Crc Introduction
CRC calculation unit RM0430 CRC calculation unit CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. -
Page 89: Crc Registers
RM0430 CRC calculation unit Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses. -
Page 90: Independent Data Register (Crc_Idr)
CRC calculation unit RM0430 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] Bits 31:8 Reserved, must be kept at reset value. -
Page 91: Crc Register Map
RM0430 CRC calculation unit 4.4.4 CRC register map Table 14. CRC calculation unit register map and reset values Offset Register CRC_DR Data register 0x00 Reset value 0xFFFF FFFF CRC_IDR Independent data register 0x04 Reset value 0x0000 CRC_CR 0x08 Reset value DocID029473 Rev 3 91/1284... -
Page 92: Power Supplies
Power controller (PWR) RM0430 Power controller (PWR) Power supplies There are two main power supply schemes: • VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal regulator disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins. -
Page 93: Independent A/D Converter Supply And Reference Voltage
RM0430 Power controller (PWR) Figure 8. Power supply overview 1. V and V must be connected to V and V , respectively. 5.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. - Page 94 Power controller (PWR) RM0430 To allow the RTC to operate even when the main digital supply (V ) is turned off, the V pin powers the following blocks: • The RTC • The LSE oscillator • PC13 to PC15 I/Os The switch to the V supply is controlled by the power-down reset embedded in the Reset block.
-
Page 95: Voltage Regulator
RM0430 Power controller (PWR) Backup domain access After reset, the backup domain (RTC registers, and RTC backup register) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows: • Access to the RTC and RTC backup registers Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 6.3.14: RCC AHB3 peripheral clock enable register... -
Page 96: Power Supply Supervisor
Power controller (PWR) RM0430 Note: For more details, refer to the voltage regulator section in the STM32F413/423 datasheet. Power supply supervisor 5.2.1 Power-on reset (POR)/power-down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V. -
Page 97: Programmable Voltage Detector (Pvd)
RM0430 Power controller (PWR) When the supply voltage (V ) drops below the selected V threshold, a device reset is generated. The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR or by an external power supervisor if the PDR is switched off through the PDR_ON pin (see Section 5.2.1: Power-on reset (POR)/power-down reset... -
Page 98: Low-Power Modes
Power controller (PWR) RM0430 Figure 11. PVD thresholds Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. - Page 99 RM0430 Power controller (PWR) Exiting low-power mode The MCU exits from Sleep and Stop modes low-power mode depending on the way the low- power mode was entered: • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
-
Page 100: Slowing Down System Clocks
Power controller (PWR) RM0430 Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. Table 15. Low-power mode summary Effect on Effect on 1.2 V Mode name Entry Wakeup Voltage regulator domain clocks domain clocks WFI or Return Sleep and Any interrupt CPU CLK OFF... -
Page 101: Sleep Mode
-M4 with FPU System Control register. If WFI or Return from ISR was used for entry: Interrupt: Refer to Table 40: Vector table for STM32F413/423 If WFE was used for entry and SEVONPEND = 0 Wakeup event: Refer to Section 10.2.3: Wakeup event management... -
Page 102: Batch Acquisition Mode
Power controller (PWR) RM0430 Table 17. Sleep-on-exit entry and exit (continued) Sleep-on-exit Description Mode exit Interrupt: refer to Table 40: Vector table for STM32F413/423 Wakeup latency None 5.3.4 Batch acquisition mode Entering BAM The BAM is entered according to Section : Entering low-power mode, when the ®... -
Page 103: Stop Mode
® Refer to the Cortex -M4 with FPU System Control register. Interrupt: refer to Table 40: Vector table for STM32F413/423 Mode exit If Flash memory wakeup time is needed, FISSR/FMSSR bits of PWR_CR register must be set None when code executed from internal SRAM... -
Page 104: Table 20. Stop Operating Modes
Power controller (PWR) RM0430 Table 20. Stop operating modes Stop mode MRLV bit LPLV bit FPDS bit LPDS bit Wakeup latency STOP MR HSI RC startup time HSI RC startup time + STOP MRFPD Flash wakeup time from Deep Power Down mode HSI RC startup time + STOP LP regulator wakeup time from LP... -
Page 105: Table 21. Stop Mode Entry And Exit
RM0430 Power controller (PWR) Section 23.3 Section 23: Window watchdog (WWDG). • Real-time clock (RTC): this is configured by the RTCEN bit in the Section 6.3.23: RCC Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Section 6.3.24: RCC clock control &... -
Page 106: Standby Mode
Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 40: Vector table for STM32F413/423. If WFE was used for entry and SEVONPEND = 0 Any EXTI lines configured in event mode. Refer to Section 10.2.3:... -
Page 107: The Stop And Standby Modes
RM0430 Power controller (PWR) Refer to Table 22 for more details on how to exit Standby mode. Table 22. Standby mode entry and exit Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP is set in Cortex -M4 with FPU System Control register, –... - Page 108 Power controller (PWR) RM0430 These RTC alternate functions can wake up the system from the Stop and Standby low- power modes. The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.
- Page 109 RM0430 Power controller (PWR) Configure the RTC to detect the tamper or time stamp event • To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to: Enable the RTC wakeup interrupt in the RTC_CR register Configure the RTC to generate the RTC wakeup event Safe RTC alternate function wakeup flag clearing sequence If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared,...
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Page 110: Power Control Registers
Power controller (PWR) RM0430 Power control registers 5.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 8000 (reset by wakeup from Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FISSR FMSSR Res. Res. Res. - Page 111 RM0430 Power controller (PWR) Bit 12 Reserved, must be kept at reset value. Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep 0: Main regulator in Voltage scale 3 when the device is in Stop mode. 1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode.
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Page 112: Pwr Power Control/Status Register (Pwr_Csr)
Power controller (PWR) RM0430 Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters deepsleep. - Page 113 RM0430 Power controller (PWR) Bit 7 EWUP2: Enable WKUP2 pin (PC0) This bit is set and cleared by software. 0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode. 1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).
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Page 114: Pwr Register Map
Power controller (PWR) RM0430 PWR register map The following table summarizes the PWR registers. Table 23. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reset value PWR_CSR 0x004 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. -
Page 115: Reset
RM0430 Reset and clock control (RCC) for STM32F413/423 Reset and clock control (RCC) for STM32F413/423 Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 6.1.1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain. -
Page 116: Power Reset
In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering the Stop mode. For further information on the user option bytes, refer to the STM32F413/423 Flash programming manual available from your ST sales office. -
Page 117: Backup Domain Reset
RM0430 Reset and clock control (RCC) for STM32F413/423 6.1.3 Backup domain reset The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. A backup domain reset is generated when one of the following events occurs:... -
Page 118: Figure 13. Clock Tree
Reset and clock control (RCC) for STM32F413/423 RM0430 Figure 13. Clock tree 1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in the device datasheet. 118/1284 DocID029473 Rev 3... -
Page 119: Hse Clock
RM0430 Reset and clock control (RCC) for STM32F413/423 The clock controller provides a high degree of flexibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like USB OTG FS, I2S and SDIO. -
Page 120: Hsi Clock
Reset and clock control (RCC) for STM32F413/423 RM0430 Figure 14. HSE/ LSE clock sources Hardware configuration OSC_OUT External clock (HI-Z) External source OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. You select this mode by setting the... -
Page 121: Pll Configuration
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the... -
Page 122: Lsi Clock
Reset and clock control (RCC) for STM32F413/423 RM0430 The LSE oscillator is switched on and off using the LSEON bit in RCC Backup domain control register (RCC_BDCR). The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. -
Page 123: Rtc/Awu Clock
RM0430 Reset and clock control (RCC) for STM32F413/423 CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that... -
Page 124: Clock-Out Capability
Reset and clock control (RCC) for STM32F413/423 RM0430 6.2.10 Clock-out capability Two microcontroller clock output (MCO) pins are available: • MCO1 You can output four different clock sources onto the MCO1 pin (PA8) using the configurable prescaler (from 1 to 5): –... -
Page 125: Figure 15. Frequency Measurement With Tim5 In Input Capture Mode
RM0430 Reset and clock control (RCC) for STM32F413/423 The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio, the better the measurement. -
Page 126: Figure 16. Frequency Measurement With Tim11 In Input Capture Mode
Reset and clock control (RCC) for STM32F413/423 RM0430 Internal/external clock measurement using TIM11 channel1 TIM11 has an input multiplexer which allows choosing whether the input capture is triggered by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in the TIM11_OR register. -
Page 127: Rcc Registers
RM0430 Reset and clock control (RCC) for STM32F413/423 RCC registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. 6.3.1 RCC clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX81 where X is undefined. - Page 128 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 18 HSEBYP: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device.
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Page 129: Rcc Pll Configuration Register (Rcc_Pllcfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.2 RCC PLL configuration register (RCC_PLLCFGR) Address offset: 0x04 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLL clock outputs according to the formulas: •... - Page 130 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written only when PLL and PLLI2S are disabled.
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Page 131: Rcc Clock Configuration Register (Rcc_Cfgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 5:0 PLLM[5:0]: Division factor for the main PLL (PLL) input clock Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO. These bits can be written only when the PLL and PLLI2S are disabled. - Page 132 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 29:27 MCO2PRE[1:0]: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset before enabling the external oscillators and the PLLs.
- Page 133 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 12:10 PPRE1[2:0]: APB Low speed prescaler (APB1) Set and cleared by software to control APB low-speed clock division factor. Caution: The software has to set these bits correctly not to exceed 50 MHz on this domain.
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Page 134: Rcc Clock Interrupt Register (Rcc_Cir)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.4 RCC clock interrupt register (RCC_CIR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access PLLI2S Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res. - Page 135 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 15:14 Reserved, must be kept at reset value. Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLLI2S lock. 0: PLLI2S lock interrupt disabled...
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Page 136: Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator... - Page 137 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 12 CRCRST: CRC reset Set and cleared by software. 0: does not reset CRC 1: resets CRC Bits 11:8 Reserved, must be kept at reset value. Bit 7 GPIOHRST: IO port H reset Set and cleared by software.
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Page 138: For Stm32F413Xx
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F413xx Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. -
Page 139: For Stm32F423Xx
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.7 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) for STM32F423xx Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. -
Page 140: Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.8 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. - Page 141 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 31 UART8RST: UART 8 reset Set and reset by software. 0: does not reset UART 8 1: resets the UART 8 Bit 30 UART7RST: UART 7 reset Set and reset by software.
- Page 142 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 20 UART5RST: UART5 reset Set and reset by software. 0: does not reset UART5 1: resets UART5 Bit 19 UART4RST: UART4 reset Set and reset by software. 0: does not reset UART4...
- Page 143 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 6 TIM12RST: TIM12 reset Set and cleared by software. 0: does not reset TIM12 1: resets TIM12 Bit 5 TIM7RST: TIM7 reset Set and cleared by software. 0: does not reset TIM7...
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Page 144: Rcc Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.10 RCC APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM10 TIM9 DFSDM2 DFSDM1 SAI1 Res. Res. - Page 145 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 15 Reserved, must be kept at reset value. Bit 14 SYSCFGRST: System configuration controller reset Set and cleared by software. 0: does not reset the System configuration controller 1: resets the System configuration controller Bit 13 SPI4RST: SPI4 reset Set and reset by software.
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Page 146: Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8RST: TIM8 reset Set and cleared by software. 0: does not reset TIM8 1: resets TIM8 Bit 0 TIM1RST: TIM1 reset Set and cleared by software. - Page 147 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 6 GPIOGEN: IO port G clock enable Set and cleared by software. 0: IO port G clock disabled 1: IO port G clock enabled Bit 5 GPIOFEN: IO port F clock enable Set and cleared by software.
- Page 148 Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.12 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) for STM32F413xx Address offset: 0x34 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res.
- Page 149 RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.13 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) for STM32F423xx Address offset: 0x34 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res.
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Page 150: Rcc Ahb3 Peripheral Clock Enable Register (Rcc_Ahb3Enr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.14 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. Res. Res. Res. Res. Res. Res. Res. Res. - Page 151 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 31 UART8EN: UART8 clock enable Set and reset by software. 0: UART8 clock disabled 1: UART8 clock enable Bit 30 UART7EN: UART7 clock enable Set and reset by software. 0: UART7 clock disabled...
- Page 152 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 20 UART5EN: UART 5 clock enable Set and RESET by software. 0: UART 5 clock disabled 1: UART 5 clock enabled Bit 19 UART4EN: UART 4 clock enable Set and cleared by software.
- Page 153 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 6 TIM12EN: TIM12 reset Set and cleared by software. 0: does not reset TIM12 1: resets TIM12 Bit 5 TIM7EN: TIM7 reset Set and cleared by software. 0: does not reset TIM7...
- Page 154 Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.16 RCC APB2 peripheral clock enable register (RCC_APB2ENR) Address offset: 0x44 Reset value: 0x0000 8000 Access: no wait state, word, half-word and byte access. TIM11 TIM10 TIM9 DFSDM2 DFSDM1 SAI1 SPI5 Res.
- Page 155 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 16 TIM9EN: TIM9 clock enable Set and cleared by software. 0: TIM9 clock disabled 1: TIM9 clock enabled Bit 15 EXITEN: Extit Apb sysctrl pfree clock enable Set and cleared by software.
- Page 156 Reset and clock control (RCC) for STM32F413/423 RM0430 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8EN: TIM8 clock enable Set and cleared by software. 0: TIM8 clock disabled 1: TIM8 clock enabled Bit 0 TIM1EN: TIM1 clock enable Set and cleared by software.
- Page 157 RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.17 RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) Address offset: 0x50 Reset value: 0x0063 90FF Access: no wait state, word, half-word and byte access. DMA2 DMA1 SRAM2 SRAM1 Res.
- Page 158 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode Set and reset by software. 0: IO port H clock disabled during sleep mode 1: IO port H clock enabled during sleep mode Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode Set and cleared by software.
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Page 159: Rcc_Ahb2Lpenr) For Stm32F413Xx
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.18 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) for STM32F413xx Address offset: 0x54 Reset value: 0x0000 00C0 Access: no wait state, word, half-word and byte access. Res. Res. -
Page 160: Rcc_Ahb2Lpenr) For Stm32F423Xx
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.19 RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) for STM32F423xx Address offset: 0x54 Reset value: 0x0000 00D0 Access: no wait state, word, half-word and byte access. Res. Res. - Page 161 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 31:2 Reserved, must be kept at reset value. Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode Set and cleared by software. 0: QUADSPI module clock disabled during Sleep mode...
- Page 162 Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.21 RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) Address offset: 0x60 Reset value: 0xFFFF CFFF Access: no wait state, word, half-word and byte access. CAN2 CAN1 I2C3 I2C2...
- Page 163 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode Set and cleared by software. 0: I2C3 clock disabled during Sleep mode 1: I2C3 clock enabled during Sleep mode Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode Set and cleared by software.
- Page 164 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 9 LPTIMER1LPEN: TIM14 clock enable during Sleep mode Set and cleared by software. 0: LPTimer 1 clock disabled during Sleep mode 1: LPTimer 1 clock enabled during Sleep mode Bit 8 TIM14LPEN: TIM14 clock enable during Sleep mode Set and cleared by software.
- Page 165 RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.22 RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) Address offset: 0x64 Reset value: 0x0317 F9F3h Access: no wait state, word, half-word and byte access. SPI5 TIM11 TIM10 TIM9...
- Page 166 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode Set and cleared by software. 0: TIM9 clock disabled during Sleep mode 1: TIM9 clock enabled during Sleep mode Bit 15 EXTITLPEN: EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode Set and cleared by software.
- Page 167 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode Set and cleared by software. 0: TIM8 clock disabled during Sleep mode 1: TIM8 clock enabled during Sleep mode Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode Set and cleared by software.
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Page 168: Rcc Backup Domain Control Register (Rcc_Bdcr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.23 RCC Backup domain control register (RCC_BDCR) Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain reset. Access: 0 wait state 3, word, half-word and byte access ≤ ≤ Wait states are inserted in case of successive accesses to this register. -
Page 169: Rcc Clock Control & Status Register (Rcc_Csr)
RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE clock is disabled. 0: LSE oscillator not bypassed... - Page 170 Reset and clock control (RCC) for STM32F413/423 RM0430 Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs.
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Page 171: Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.25 RCC spread spectrum clock generation register (RCC_SSCGR) Address offset: 0x80 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. The spread spectrum clock generation is available only for the main PLL. -
Page 172: Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.26 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) Address offset: 0x84 Reset value: 0x2400 3010 Access: no wait state, word, half-word and byte access. This register is used to configure the PLLI2S clock outputs according to the formulas: •... - Page 173 RM0430 Reset and clock control (RCC) for STM32F413/423 Bit 22 PLLI2SSRC: PLLI2S entry clock source Set and cleared by software to select PLLI2S clock source. This bit can be written only when PLLI2S is disabled. 0: HSE or HSI depending on PLLSRC of PLLCFGR 1: external AFI clock (CK_I2S_EXT) selected as PLL clock entry Bits 21:15 Reserved, must be kept at reset value.
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Page 174: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.27 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) Address offset: 0x8C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. CKDFSD Res. Res. I2S2RC[1:0] I2S1RC[1:0] TIMPRE SAI1BSRC SAI1ASRC Res. - Page 175 RM0430 Reset and clock control (RCC) for STM32F413/423 Bits 23:22 SAII1BSRC: SAI1 B clock selection Set and reset by software. 00: PLLI2S_R divided (R2) as SAI1 B clock 01: I2S_CLIN as SAI1 B clock 00: PLL_R divided (R1) as SAI1 B clock...
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Page 176: Rcc Clocks Gated Enable Register (Ckgatenr)
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.28 RCC clocks gated enable register (CKGATENR) Address offset: 0x90 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. This register allows to enable or disable the clock gating for the specified IPs. -
Page 177: Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr2)
RM0430 Reset and clock control (RCC) for STM32F413/423 6.3.29 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2) Address offset: 0x94 Reset value: 0x0000 0000 This register allows to enable or disable the clock gating for the specified IPs. LPTIMER1 SDIO CK48M I2CFMP1 Res. -
Page 178: Rcc Register Map
Reset and clock control (RCC) for STM32F413/423 RM0430 6.3.30 RCC register map Table 24 gives the register map and reset values Table 24. RCC register map and reset values for STM32F413/423 Addr. Register offset name RCC_ 0x00 HSICAL[7:0] HSITRIM[4:0] RCC_... - Page 179 RM0430 Reset and clock control (RCC) for STM32F413/423 Table 24. RCC register map and reset values for STM32F413/423 (continued) Addr. Register offset name RCC_ 0x38 AHB3ENR 0x3C Reserved RCC_ 0x40 APB1ENR RCC_ 0x44 APB2ENR 0x48 Reserved 0x4C Reserved RCC_ 0x50...
- Page 180 Reset and clock control (RCC) for STM32F413/423 RM0430 Table 24. RCC register map and reset values for STM32F413/423 (continued) Addr. Register offset name RCC_ 0x80 INCSTEP[14:0] MODPER[11:0] SSCGR RCC_ 0x84 PLLI2SN[8:0]] PLLI2SM[5:0] PLLI2SCFGR 0x88 Reserved RCC_ 0x8C PLLDIVR[4:0]] PLLI2SDIVR[4:0]] DCKCFGR...
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Page 181: General-Purpose I/Os (Gpio)
RM0430 General-purpose I/Os (GPIO) General-purpose I/Os (GPIO) GPIO introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL). -
Page 182: Table 25. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0430 Figure 17 show the basic structure of a 5 V tolerant I/O port bit. Table 25 gives the possible port bit configurations. Figure 17. Basic structure of a five-volt tolerant I/O port bit 1. V is a potential specific to five-volt tolerant I/Os and different from V DD_FT Table 25. -
Page 183: General-Purpose I/O (Gpio)
RM0430 General-purpose I/Os (GPIO) Table 25. Port bit configuration table (continued) MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [B:A] [1:0] PP + PU PP + PD Reserved SPEED [B:A] OD + PU OD + PD Reserved Input Floating Input Input Reserved (input floating) Input/output Analog... -
Page 184: I/O Pin Multiplexer And Mapping
Cortex -M4 with FPU EVENTOUT is mapped on AF15 This structure is shown in Figure 18: Selecting an alternate function on STM32F413/423 below. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. -
Page 185: Table 26. Flexible Swj-Dp Pin Assignment
RM0430 General-purpose I/Os (GPIO) Table 26. Flexible SWJ-DP pin assignment SWJ I/O pin assigned PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ JTDI JTDO NJTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset state Full SWJ (JTAG-DP + SW-DP) but without NJTRST JTAG-DP Disabled and SW-DP Enabled... -
Page 186: Figure 18. Selecting An Alternate Function On Stm32F413/423
General-purpose I/Os (GPIO) RM0430 Figure 18. Selecting an alternate function on STM32F413/423 186/1284 DocID029473 Rev 3... -
Page 187: I/O Port Control Registers
RM0430 General-purpose I/Os (GPIO) 7.3.3 I/O port control registers Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). -
Page 188: I/O Alternate Function Input/Output
General-purpose I/Os (GPIO) RM0430 The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A...H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits. -
Page 189: Output Configuration
RM0430 General-purpose I/Os (GPIO) Figure 19. Input floating/pull up/pull down configurations 7.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –... -
Page 190: Alternate Function Configuration
General-purpose I/Os (GPIO) RM0430 Figure 20. Output configuration 7.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured as open-drain or push-pull • The output buffer is driven by the signal coming from the peripheral (transmitter enable and data) •... -
Page 191: Analog Configuration
RM0430 General-purpose I/Os (GPIO) 7.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •... -
Page 192: Selection Of Rtc Additional Functions
General-purpose I/Os (GPIO) RM0430 7.3.15 Selection of RTC additional functions The STM32F4xx feature one GPIO pin RTC_AF1 that can be used for the detection of a tamper or time stamp event, or RTC_ALARM, or RTC_CALIB RTC outputs. • The RTC_AF1 (PC13) can be used for the following purposes: RTC_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register •... -
Page 193: Gpio Registers
RM0430 General-purpose I/Os (GPIO) GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits). 7.4.1 GPIO port mode register (GPIOx_MODER) (x = A...H) Address offset: 0x00... - Page 194 General-purpose I/Os (GPIO) RM0430 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A...H) Address offset: 0x08 Reset values: • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports OSPEEDR15 OSPEEDR14 OSPEEDR13 OSPEEDR12 OSPEEDR11 OSPEEDR10...
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Page 195: Gpio Port Input Data Register (Gpiox_Idr) (X = A...h)
RM0430 General-purpose I/Os (GPIO) 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A...H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. - Page 196 General-purpose I/Os (GPIO) RM0430 Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority.
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Page 197: Gpio Alternate Function Low Register (Gpiox_Afrl) (X = A...h)
RM0430 General-purpose I/Os (GPIO) Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK[16]: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. -
Page 198: Gpio Register Map
General-purpose I/Os (GPIO) RM0430 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A...H) Address offset: 0x24 Reset value: 0x0000 0000 AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Bits 31:0 AFRHy: Alternate function selection for port x bit y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRHy selection: 0000: AF0... - Page 199 RM0430 General-purpose I/Os (GPIO) Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_ OTYPER 0x04 (where x = A...H) Reset value GPIOx_ OSPEEDR (where x = 0x08 C...H) Reset value GPIOA_ OSPEEDER 0x08 Reset value GPIOB_ OSPEEDR 0x08 Reset value GPIOA_PUPDR...
- Page 200 General-purpose I/Os (GPIO) RM0430 Table 28. GPIO register map and reset values (continued) Offset Register GPIOx_LCKR (where x = A...H) 0x1C Reset value GPIOx_AFRL AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] (where x = A...H) 0x20 Reset value GPIOx_AFRH AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]...
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Page 201: I/O Compensation Cell
RM0430 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area and manage the external interrupt line connection to the GPIOs. I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O t commutation to reduce the I/O noise on power... -
Page 202: Syscfg Peripheral Mode Configuration Register (Syscfg_Pmc)
System configuration controller (SYSCFG) RM0430 Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection Set and cleared by software. This bit controls the memory internal mapping at address 0x0000 0000. After reset these bits take the value selected by the Boot pins. -
Page 203: Syscfg External Interrupt Configuration Register
RM0430 System configuration controller (SYSCFG) 8.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved, must be kept at reset value. - Page 204 System configuration controller (SYSCFG) RM0430 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
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Page 205: Syscfg Configuration Register 2 (Syscfg_Cfgr2)
RM0430 System configuration controller (SYSCFG) 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value. -
Page 206: Compensation Cell Control Register (Syscfg_Cmpcr)
System configuration controller (SYSCFG) RM0430 Bit 2 PVDL: PVD lock This bit is set by software. It can be cleared only by a system reset. It enables and locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the PVDE and PVDS[2:0] bits of PWR_CR register. -
Page 207: Syscfg Configuration Register (Syscfg_Cfgr)
RM0430 System configuration controller (SYSCFG) 8.2.9 SYSCFG configuration register (SYSCFG_CFGR) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. - Page 208 System configuration controller (SYSCFG) RM0430 Bit 16 DFSDM2_CK37SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 (DM3 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping) 0: The gated clock is distributed to CkIn3 (DM3 = 0) 1: The gated clock is distributed to CkIn7 (DM3 = 1) Bit 15 DFSDM2_CK26SEL: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2...
- Page 209 RM0430 System configuration controller (SYSCFG) Bit 4 DFSDM1_CK02SEL: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC2 (DM2 demultiplexer on Figure 81: Multi-channel delay block for pulse skipping) 0: The gated clock is distributed to CkIn0 (DM2 = 0) 1: The gated clock is distributed to CkIn2 (DM2 = 1) Bit 3 DFSDM1_D2SEL: Source selection for DatIn2 of DFSDM1 (M8 multiplexer on...
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Page 210: Syscfg Register Map
System configuration controller (SYSCFG) RM0430 8.2.11 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 29. SYSCFG register map and reset values Offset Register SYSCFG_ MEMRMP 0x00 Reset value SYSCFG_PMC 0x04 Reset value SYSCFG_EXTICR1 EXTI3[3:0] EXTI2[3:0]... -
Page 211: Dma Introduction
RM0430 Direct memory access controller (DMA) Direct memory access controller (DMA) DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be quickly moved by DMA without any CPU action. - Page 212 Direct memory access controller (DMA) RM0430 • Each stream also supports software trigger for memory-to-memory transfers (only available for the DMA2 controller) • Each stream request can be selected via among up to 16 possible channel requests. This selection is software-configurable and allows several peripherals to initiate DMA requests •...
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Page 213: Dma Functional Description
RM0430 Direct memory access controller (DMA) DMA functional description 9.3.1 DMA block diagram Figure 23 shows the block diagram of a DMA. Figure 23. DMA block diagram 9.3.2 DMA overview The DMA controller performs direct memory transfer: as an AHB master, it can take the control of the AHB bus matrix to initiate AHB transactions. -
Page 214: Dma Transactions
Direct memory access controller (DMA) RM0430 9.3.3 DMA transactions A DMA transaction consists of a sequence of a given number of data transfers. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software- programmable. -
Page 215: Table 30. Dma1 Request Mapping
RM0430 Direct memory access controller (DMA) Table 30. DMA1 request mapping Peripheral Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 requests Channel 0 SPI3_RX I2C1_TX SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPI3_TX Channel 1 I2C1_RX I2C3_RX TIM7_UP... -
Page 216: Arbiter
Direct memory access controller (DMA) RM0430 9.3.5 Arbiter An arbiter manages the 8 DMA stream requests based on their priority for each of the two AHB master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. Priorities are managed in two stages: •... -
Page 217: Figure 25. Peripheral-To-Memory Mode
RM0430 Direct memory access controller (DMA) When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register) is a half-word or a word, respectively, the peripheral or memory address written into the DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word address boundary, respectively. -
Page 218: Figure 26. Memory-To-Peripheral Mode
Direct memory access controller (DMA) RM0430 Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined threshold level, the FIFO is fully reloaded with data from the memory. The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in the DMA_SxCR register is cleared by software. -
Page 219: Pointer Incrementation
RM0430 Direct memory access controller (DMA) The stream has access to the AHB source or destination port only if the arbitration of the corresponding stream is won. This arbitration is performed using the priority defined for each stream using the PL[1:0] bits in the DMA_SxCR register. Note: When memory-to-memory mode is used, the Circular and direct modes are not allowed. -
Page 220: Circular Mode
Direct memory access controller (DMA) RM0430 9.3.9 Circular mode The Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR register. When the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the DMA requests continue to be served. -
Page 221: Programmable Data Width, Packing/Unpacking, Endianness
RM0430 Direct memory access controller (DMA) memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in accordance with one of the two above conditions. For all the other modes (except the Double buffer mode), the memory address registers are write-protected as soon as the stream is enabled. -
Page 222: Table 34. Packing/Unpacking & Endian Behavior (Bit Pinc = Minc = 1)
Direct memory access controller (DMA) RM0430 Table 34. Packing/unpacking & endian behavior (bit PINC = MINC = 1) Number Peripheral port address / byte lane of data Memory Memory port Peripheral memory peripheral items to transfer address / byte transfer port port PINCOS = 1... -
Page 223: Single And Burst Transfers
RM0430 Direct memory access controller (DMA) 9.3.12 Single and burst transfers The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. The size of the burst is configured by software independently for the two AHB ports by using the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register. -
Page 224: Table 36. Fifo Threshold Configurations
Direct memory access controller (DMA) RM0430 Figure 28. FIFO structure FIFO threshold and burst configuration Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The content pointed by the FIFO threshold must exactly match an integer number of memory burst transfers. - Page 225 RM0430 Direct memory access controller (DMA) Table 36. FIFO threshold configurations (continued) MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16 forbidden 1 burst of 4 beats forbidden Half-word forbidden Full 2 bursts of 4 beats 1 burst of 8 beats forbidden forbidden Word...
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Page 226: Dma Transfer Completion
Direct memory access controller (DMA) RM0430 undesired value. The software may read the DMA_SxNDTR register to determine the memory area that contains the good data (start address and last address). If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB memory port), single transactions will be generated to complete the FIFO flush. -
Page 227: Dma Transfer Suspension
RM0430 Direct memory access controller (DMA) 9.3.15 DMA transfer suspension At any time, a DMA transfer can be suspended to be restarted later on or to be definitively disabled before the end of the DMA transfer. There are two cases: •... -
Page 228: Summary Of The Possible Dma Configurations
Direct memory access controller (DMA) RM0430 triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the corresponding stream is set in the status register to indicate the DMA completion. To know the number of data items transferred during the DMA transfer, read the DMA_SxNDTR register and apply the following formula: –... -
Page 229: Stream Configuration Procedure
RM0430 Direct memory access controller (DMA) 9.3.18 Stream configuration procedure The following sequence should be followed to configure a DMA stream x (where x is the stream number): If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register, then read this bit in order to confirm that there is no ongoing stream operation. -
Page 230: Error Management
Direct memory access controller (DMA) RM0430 9.3.19 Error management The DMA controller can detect the following errors: • Transfer error: the transfer error interrupt flag (TEIFx) is set when: – A bus error occurs during a DMA read or a write access –... -
Page 231: Dma Interrupts
RM0430 Direct memory access controller (DMA) DMA interrupts For each DMA stream, an interrupt can be produced on the following events: • Half-transfer reached • Transfer complete • Transfer error • FIFO error (overrun, underrun or FIFO level error) • Direct mode error Separate interrupt enable control bits are available for flexibility as shown in Table... -
Page 232: Dma Registers
Direct memory access controller (DMA) RM0430 DMA registers The DMA registers have to be accessed by words (32 bits). 9.5.1 DMA low interrupt status register (DMA_LISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res. -
Page 233: Dma High Interrupt Status Register (Dma_Hisr)
RM0430 Direct memory access controller (DMA) 9.5.2 DMA high interrupt status register (DMA_HISR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. TCIF7 HTIF7 TEIF7 DMEIF7 Res. FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6 Res. FEIF6 Res. Res. Res. Res. TCIF5 HTIF5 TEIF5... -
Page 234: Dma Low Interrupt Flag Clear Register (Dma_Lifcr)
Direct memory access controller (DMA) RM0430 9.5.3 DMA low interrupt flag clear register (DMA_LIFCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. CTCIF3 CHTIF3 CTEIF3 CDMEIF3 Res. CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2 Res. CFEIF2 Res. Res. Res. Res. -
Page 235: Dma Stream X Configuration Register (Dma_Sxcr) (X = 0..7)
RM0430 Direct memory access controller (DMA) Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register Bits 23, 17, 7, 1 Reserved, must be kept at reset value. Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4) Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register 9.5.5... - Page 236 Direct memory access controller (DMA) RM0430 Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration These bits are set and cleared by software. 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) These bits are protected and can be written only if EN is ‘0’...
- Page 237 RM0430 Direct memory access controller (DMA) Bits 12:11 PSIZE[1:0]: Peripheral data size These bits are set and cleared by software. 00: Byte (8-bit) 01: Half-word (16-bit) 10: Word (32-bit) 11: reserved These bits are protected and can be written only if EN is ‘0’ Bit 10 MINC: Memory increment mode This bit is set and cleared by software.
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Page 238: Dma Stream X Number Of Data Register (Dma_Sxndtr) (X = 0..7)
Direct memory access controller (DMA) RM0430 Bit 2 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 1 DMEIE: Direct mode error interrupt enable This bit is set and cleared by software. 0: DME interrupt disabled 1: DME interrupt enabled Bit 0 EN: Stream enable / flag stream ready when read low... -
Page 239: Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7)
RM0430 Direct memory access controller (DMA) 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) Address offset: 0x18 + 0x18 × stream number Reset value: 0x0000 0000 PAR[31:16] PAR[15:0] Bits 31:0 PAR[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register. -
Page 240: Dma Stream X Fifo Control Register (Dma_Sxfcr) (X = 0..7)
Direct memory access controller (DMA) RM0430 Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode) Base address of Memory area 1 from/to which the data will be read/written. This register is used only for the Double buffer mode. These bits are write-protected. - Page 241 RM0430 Direct memory access controller (DMA) Bit 2 DMDIS: Direct mode disable This bit is set and cleared by software. It can be set by hardware. 0: Direct mode enabled 1: Direct mode disabled This bit is protected and can be written only if EN is ‘0’. This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’...
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Page 242: Dma Register Map
Direct memory access controller (DMA) RM0430 9.5.11 DMA register map Table 39 summarizes the DMA registers. Table 39. DMA register map and reset values Offset Register DMA_LISR 0x0000 Reset value DMA_HISR 0x0004 Reset value DMA_LIFCR 0x0008 Reset value DMA_HIFCR 0x000C Reset value DMA_S0CR 0x0010... - Page 243 RM0430 Direct memory access controller (DMA) Table 39. DMA register map and reset values (continued) Offset Register DMA_S1PAR PA[31:0] 0x0030 Reset value DMA_S1M0AR M0A[31:0] 0x0034 Reset value DMA_S1M1AR M1A[31:0] 0x0038 Reset value DMA_S1FCR FS[2:0] [1:0] 0x003C Reset value DMA_S2CR 0x0040 Reset value DMA_S2NDTR NDT[15:.]...
- Page 244 Direct memory access controller (DMA) RM0430 Table 39. DMA register map and reset values (continued) Offset Register DMA_S3M1AR M1A[31:0] 0x0068 Reset value DMA_S3FCR FS[2:0] [1:0] 0x006C Reset value DMA_S4CR 0x0070 Reset value DMA_S4NDTR NDT[15:.] 0x0074 Reset value DMA_S4PAR PA[31:0] 0x0078 Reset value DMA_S4M0AR M0A[31:0]...
- Page 245 RM0430 Direct memory access controller (DMA) Table 39. DMA register map and reset values (continued) Offset Register DMA_S6M0AR M0A[31:0] 0x00AC Reset value DMA_S6M1AR M1A[31:0] 0x00B0 Reset value DMA_S6FCR FS[2:0] [1:0] 0x00B4 Reset value DMA_S7CR 0x00B8 Reset value DMA_S7NDTR NDT[15:.] 0x00BC Reset value DMA_S7PAR PA[31:0]...
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Page 246: Nested Vectored Interrupt Controller (Nvic)
SysTick clock set to 10.5 MHz (HCLK/8, with HCLK set to 84 MHz). 10.1.3 Interrupt and exception vectors Table 40, for the vector table for the STM32F413/423 devices. 10.2 External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. -
Page 247: Table 40. Vector Table For Stm32F413/423
RM0430 Interrupts and events Table 40. Vector table for STM32F413/423 Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt, Clock Security fixed 0x0000 0008 System fixed HardFault All class of fault 0x0000 000C... - Page 248 Interrupts and events RM0430 Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority settable DMA1_Stream4 DMA1 Stream4 global interrupt 0x0000 007C settable DMA1_Stream5 DMA1 Stream5 global interrupt 0x0000 0080 settable DMA1_Stream6 DMA1 Stream6 global interrupt 0x0000 0084...
- Page 249 RM0430 Interrupts and events Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority EXTI Line 17 interrupt / EXTI17 / settable 0x0000 00E4 RTC Alarms (A and B) through EXTI line RTC Alarm interrupt EXTI Line 18 interrupt / USB On-The-Go FS...
- Page 250 Interrupts and events RM0430 Table 40. Vector table for STM32F413/423 (continued) Type of Acronym Description Address priority settable OTG_FS USB On The Go FS global interrupt 0x0000 014C settable DMA2_Stream5 DMA2 Stream5 global interrupt 0x0000 0150 settable DMA2_Stream6 DMA2 Stream6 global interrupt...
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Page 251: Exti Main Features
RM0430 Interrupts and events 10.2.1 EXTI main features The main features of the EXTI controller are the following: • independent trigger and mask on each interrupt/event line • dedicated status bit for each interrupt line • generation of up to 23 software event/interrupt requests •... - Page 252 Interrupts and events RM0430 IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.
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Page 253: Functional Description
RM0430 Interrupts and events 10.2.4 Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. -
Page 254: External Interrupt/Event Line Mapping
Interrupts and events RM0430 10.2.5 External interrupt/event line mapping Up to STM32F413/423 are connected to the 16 external interrupt/event lines in the following manner: Figure 30. External interrupt/event GPIO mapping The five other EXTI lines are connected as follows: •... -
Page 255: Interrupt Mask Register (Exti_Imr)
RM0430 Interrupts and events 10.3 registers EXTI Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. -
Page 256: Rising Trigger Selection Register (Exti_Rtsr)
Interrupts and events RM0430 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 TR[22:21]: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line... -
Page 257: Falling Trigger Selection Register (Exti_Ftsr)
RM0430 Interrupts and events 10.3.4 Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. TR22 TR21 Res. Res. TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:21 TR[22:21]: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. -
Page 258: Software Interrupt Event Register (Exti_Swier)
Interrupts and events RM0430 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER SWIER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER... -
Page 259: Pending Register (Exti_Pr)
RM0430 Interrupts and events 10.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. PR22 PR21 Res. Res. PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PR15 PR14 PR13 PR12 PR11 PR10 rc_w1 rc_w1... -
Page 260: Exti Register Map
Interrupts and events RM0430 10.3.7 EXTI register map Table 41 gives the EXTI register map and the reset values. Table 41. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] [22:21] 0x00 Reset value EXTI_EMR MR[18:0] [22:21] 0x04 Reset value EXTI_RTSR... -
Page 261: Flexible Static Memory Controller (Fsmc)
RM0430 Flexible static memory controller (FSMC) Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes one memory controller: • The NOR/PSRAM memory controller 11.1 FSMC main features The FSMC functional block makes the interface with: synchronous and asynchronous static memories. -
Page 262: Block Diagram
Flexible static memory controller (FSMC) RM0430 11.2 Block diagram The FSMC consists of the following main blocks: • The AHB interface (including the FSMC configuration registers) • The NOR Flash/PSRAM/SRAM controller The block diagram is shown in the figure below. Figure 31. -
Page 263: Ahb Interface
RM0430 Flexible static memory controller (FSMC) 11.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. -
Page 264: External Device Address Mapping
Flexible static memory controller (FSMC) RM0430 transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length. -
Page 265: Nor Flash/Psram Controller
RM0430 Flexible static memory controller (FSMC) The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 43. -
Page 266: External Memory Interface Signals
Flexible static memory controller (FSMC) RM0430 and synchronous accesses depending on the CCKEN bit configuration in the FSMC_BCR1 register: • If the CCLKEN bit is reset, the FSMC generates the clock (CLK) only during synchronous accesses (Read/write transactions). • If the CCLKEN bit is set, the FSMC generates a continuous clock during asynchronous and synchronous accesses. -
Page 267: Table 45. Non-Multiplexed I/O Nor Flash Memory
RM0430 Flexible static memory controller (FSMC) NOR Flash memory, non-multiplexed I/Os Table 45. Non-multiplexed I/O NOR Flash memory FSMC signal name Function Clock (for synchronous access) A[25:0] Address bus D[15:0] Bidirectional data bus NE[x] Chip Select, x = 1..4 Output enable Write enable Latch enable (this signal is called address NL(=NADV) -
Page 268: Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0430 Table 47. Non-multiplexed I/Os PSRAM/SRAM (continued) FSMC signal Function name NE[x] Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid only for PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FSMC NBL[1:0]... -
Page 269: Table 49. Nor Flash/Psram: Example Of Supported Memories And Transactions
RM0430 Flexible static memory controller (FSMC) Table 49. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Asynchronous Asynchronous NOR Flash Asynchronous Split into 2 FSMC accesses (muxed I/Os Asynchronous Split into 2 FSMC accesses and nonmuxed... -
Page 270: General Timing Rules
Flexible static memory controller (FSMC) RM0430 11.5.3 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In synchronous mode (read or write), all output signals change on the rising edge of HCLK. -
Page 271: Figure 33. Mode1 Read Access Waveforms
RM0430 Flexible static memory controller (FSMC) Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers. Figure 33. Mode1 read access waveforms Figure 34. -
Page 272: Table 50. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). Table 50. -
Page 273: Figure 35. Modea Read Access Waveforms
RM0430 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 35. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 36. ModeA write access waveforms DocID029473 Rev 3 273/1284... -
Page 274: Table 52. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 52. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW... -
Page 275: Table 54. Fsmc_Bwtrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 54. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST HCLK cycles) for write 15:8 DATAST... -
Page 276: Figure 38. Mode2 Write Access Waveforms
Flexible static memory controller (FSMC) RM0430 Figure 38. Mode2 write access waveforms Figure 39. ModeB write access waveforms The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). 276/1284 DocID029473 Rev 3... -
Page 277: Table 55. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 55. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000 WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature. -
Page 278: Table 57. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 57. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 0x1 if extended mode is set 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the access second phase (DATAST HCLK cycles) for 15:8 DATAST... -
Page 279: Table 58. Fsmc_Bcrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Figure 41. ModeC write access waveforms The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 58. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000... -
Page 280: Table 59. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Table 58. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 59. FSMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24... -
Page 281: Figure 42. Moded Read Access Waveforms
RM0430 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 42. ModeD read access waveforms Figure 43. ModeD write access waveforms DocID029473 Rev 3 281/1284... -
Page 282: Table 61. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 61. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000... -
Page 283: Table 63. Fsmc_Bwtrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 63. FSMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK). Duration of the second access phase (DATAST + 1 HCLK cycles) for 15:8 DATAST... -
Page 284: Table 64. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Figure 45. Muxed write access waveforms The difference with ModeD is the drive of the lower address byte(s) on the data bus. Table 64. FSMC_BCRx bit fields Bit number Bit name Value to set 31:22 Reserved 0x000... -
Page 285: Table 65. Fsmc_Btrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 64. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 65. FSMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29:28... -
Page 286: Figure 46. Asynchronous Wait During A Read Access Waveforms
Flexible static memory controller (FSMC) RM0430 The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥... -
Page 287: Synchronous Transactions
RM0430 Flexible static memory controller (FSMC) Figure 47. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. 11.5.5 Synchronous transactions The memory clock, FSMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FSMC_CLK divider ratio max CLKDIV... - Page 288 Flexible static memory controller (FSMC) RM0430 Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FSMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
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Page 289: Figure 48. Wait Configuration Waveforms
RM0430 Flexible static memory controller (FSMC) Figure 48. Wait configuration waveforms DocID029473 Rev 3 289/1284... -
Page 290: Table 66. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 66. -
Page 291: Table 67. Fsmc_Btrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 66. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN... -
Page 292: Table 68. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0430 Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 68. -
Page 293: Table 69. Fsmc_Btrx Bit Fields
RM0430 Flexible static memory controller (FSMC) Table 68. FSMC_BCRx bit fields (continued) Bit number Bit name Value to set WREN WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP... -
Page 294: Nor/Psram Controller Registers
Flexible static memory controller (FSMC) RM0430 11.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. - Page 295 RM0430 Flexible static memory controller (FSMC) Bits 18:16 CPSIZE[2:0]: CRAM page size. These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FSMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).
- Page 296 Flexible static memory controller (FSMC) RM0430 Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable.
- Page 297 RM0430 Flexible static memory controller (FSMC) Res. Res. ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
- Page 298 Flexible static memory controller (FSMC) RM0430 Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ).
- Page 299 RM0430 Flexible static memory controller (FSMC) Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 33 Figure 45), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
- Page 300 Flexible static memory controller (FSMC) RM0430 Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D...
- Page 301 RM0430 Flexible static memory controller (FSMC) Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 33 Figure 45), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
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Page 302: Fsmc Register Map
Flexible static memory controller (FSMC) RM0430 11.6 FSMC register map Table 70. FSMC register map Offset Register CPSIZE MWID MTYP FSMC_BCR1 [2:0] [1:0] [1:0] 0x00 Reset value CPSIZE MWID MTYP FSMC_BCR2 [2:0] [1:0] [1:0] 0x08 Reset value CPSIZE MWID MTYP FSMC_BCR3 [2:0] [1:0]... - Page 303 RM0430 Flexible static memory controller (FSMC) Table 70. FSMC register map (continued) Offset Register FSMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value FSMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x11C Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. DocID029473 Rev 3 303/1284...
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Page 304: Introduction
Quad-SPI interface (QUADSPI) RM0430 Quad-SPI interface (QUADSPI) 12.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •... -
Page 305: Quadspi Pins
RM0430 Quad-SPI interface (QUADSPI) Figure 52. QUADSPI block diagram when dual-flash mode is enabled 12.3.2 QUADSPI pins Table 71 lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11 for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode. Table 71. -
Page 306: Quadspi Command Sequence
Quad-SPI interface (QUADSPI) RM0430 12.3.3 QUADSPI Command sequence The QUADSPI communicates with the Flash memory using commands. Each command can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phase must be present. - Page 307 RM0430 Quad-SPI interface (QUADSPI) Alternate-bytes phase In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control the mode of operation. The number of alternate bytes to be sent is configured in the ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in the QUADSPI_ABR register.
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Page 308: Quadspi Signal Interface Protocol Modes
Quad-SPI interface (QUADSPI) RM0430 mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14] register. When DMODE = 00, the data phase is skipped, and the command sequence finishes immediately by raising nCS. This configuration must only be used in only indirect write mode. -
Page 309: Figure 54. An Example Of A Ddr Command In Quad Mode
RM0430 Quad-SPI interface (QUADSPI) SDR mode By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single data rate (SDR) mode. In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these signals transition only with the falling edge of CLK. When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also send the data using CLK’s falling edge. -
Page 310: Quadspi Indirect Mode
Quad-SPI interface (QUADSPI) RM0430 The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect the total Flash memory capacity, which is double the size of one individual component. If address X is even, then the byte which the QUADSPI gives for address X is the byte at the address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the byte at the address X/2 of FLASH 2. -
Page 311: Quadspi Status Flag Polling Mode
RM0430 Quad-SPI interface (QUADSPI) is set when the limit of the external SPI memory is reached according to the Flash memory size defined in the QUADSPI_CR. Triggering the start of a command Essentially, a command starts as soon as firmware gives the last information that is necessary for this command. -
Page 312: Quadspi Memory-Mapped Mode
Quad-SPI interface (QUADSPI) RM0430 The accesses to the Flash memory begin in the same way as in indirect read mode: if no address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is written. -
Page 313: Quadspi Flash Memory Configuration
RM0430 Quad-SPI interface (QUADSPI) nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed without any access since when the FIFO becomes full with prefetch data. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the peripheral is disabled. -
Page 314: Quadspi Usage
Quad-SPI interface (QUADSPI) RM0430 DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate bytes are sent on both clock edges and the data are sent/received on both clock edges. Regardless of the DDRM bit setting, instructions are always sent in SDR mode. The DMA requests are enabled setting the DMAEN bit. - Page 315 RM0430 Quad-SPI interface (QUADSPI) When writing the control register (QUADSPI_CR) the user specifies the following settings: • The enable bit (EN) set to ‘1’ • The DMA enable bit (DMAEN) for transferring data to/from RAM • Timeout counter enable bit (TCEN) •...
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Page 316: Sending The Instruction Only Once
Quad-SPI interface (QUADSPI) RM0430 In case of match, the status match flag is set and an interrupt is generated if enabled, and the QUADSPI can be automatically stopped if the AMPS bit is set. In any case, the latest retrieved value is available in the QUADSPI_DR. Memory-mapped mode In memory-mapped mode, the external Flash memory is seen as internal memory but with some latency during accesses. -
Page 317: Quadspi Busy Bit And Abort Functionality
RM0430 Quad-SPI interface (QUADSPI) 12.3.14 QUADSPI busy bit and abort functionality Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is automatically set in the QUADSPI_SR. In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested command sequence and the FIFO is empty. -
Page 318: Figure 57. Ncs When Ckmode = 1 In Ddr Mode (T = Clk Period)
Quad-SPI interface (QUADSPI) RM0430 When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 57. -
Page 319: Quadspi Interrupts
RM0430 Quad-SPI interface (QUADSPI) 12.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 72. QUADSPI interrupt requests Interrupt event Event flag Enable control bit... -
Page 320: Quadspi Registers
Quad-SPI interface (QUADSPI) RM0430 12.5 QUADSPI registers 12.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. FTHRES FSEL Res. SSHIFT TCEN DMAEN ABORT Bits 31: 24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1). - Page 321 RM0430 Quad-SPI interface (QUADSPI) Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
- Page 322 Quad-SPI interface (QUADSPI) RM0430 Bit 4 SSHIFT: Sample shift By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the Flash memory. This bit allows the data is to be sampled later in order to account for external signal delays.
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Page 323: Quadspi Device Configuration Register (Quadspi_Dcr)
RM0430 Quad-SPI interface (QUADSPI) 12.5.2 QUADSPI device configuration register (QUADSPI_DCR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FSIZE Res. Res. Res. Res. Res. CSHT Res. Res. Res. Res. Res. Res. -
Page 324: Quadspi Status Register (Quadspi_Sr)
Quad-SPI interface (QUADSPI) RM0430 12.5.3 QUADSPI status register (QUADSPI_SR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLEVEL[5:0] Res. Res. BUSY Bits 31:14 Reserved, must be kept at reset value. Bits 13:8 FLEVEL[5:0]: FIFO level This field gives the number of valid bytes which are being held in the FIFO. -
Page 325: Quadspi Flag Clear Register (Quadspi_Fcr)
RM0430 Quad-SPI interface (QUADSPI) 12.5.4 QUADSPI flag clear register (QUADSPI_FCR) Address offset: 0x000C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 326: Quadspi Communication Configuration Register (Quadspi_Ccr)
Quad-SPI interface (QUADSPI) RM0430 Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE. - Page 327 RM0430 Quad-SPI interface (QUADSPI) Bit 28 SIOO: Send instruction only once mode Section 12.3.12: Sending the instruction only once on page 316. This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
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Page 328: Quadspi Address Register (Quadspi_Ar)
Quad-SPI interface (QUADSPI) RM0430 Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line... -
Page 329: Quadspi Alternate Bytes Registers (Quadspi_Abr)
RM0430 Quad-SPI interface (QUADSPI) 12.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) Address offset: 0x001C Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. -
Page 330: Quadspi Polling Status Mask Register (Quadspi _Psmkr)
Quad-SPI interface (QUADSPI) RM0430 12.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) Address offset: 0x0024 Reset value: 0x0000 0000 MASK[31:16] MASK[15:0] Bits 31: 0 MASK[31: 0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic... -
Page 331: Quadspi Polling Interval Register (Quadspi _Pir)
RM0430 Quad-SPI interface (QUADSPI) 12.5.12 QUADSPI polling interval register (QUADSPI _PIR) Address offset: 0x002C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INTERVAL[15:0] Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 INTERVAL[15: 0]: Polling interval Number of CLK cycles between to read during automatic polling phases. -
Page 332: Quadspi Register Map
Quad-SPI interface (QUADSPI) RM0430 12.5.14 QUADSPI register map Table 73. QUADSPI register map and reset values Offset Register FTHRES QUADSPI_CR PRESCALER[7:0] [4:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[6:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010... -
Page 333: Adc Introduction
RM0430 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 13.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the V channel. -
Page 334: Adc On-Off Control
Analog-to-digital converter (ADC) RM0430 Table 74. ADC pins Name Signal type Remarks Input, analog reference The lower/negative reference voltage for the ADC, REF– negative REF– Input, analog supply Ground for analog power supply equal to V ground ADCx_IN[15:0] Analog input signals 16 analog input channels 13.3.1 ADC on-off control... -
Page 335: Single Conversion Mode
RM0430 Analog-to-digital converter (ADC) Temperature sensor, V and V internal channels REFINT • The temperature sensor is internally connected to ADC1_IN18 channel which is shared with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a time. When the temperature sensor and VBAT conversion are set simultaneously, only the VBAT conversion is performed. -
Page 336: Timing Diagram
Analog-to-digital converter (ADC) RM0430 13.3.6 Timing diagram As shown in Figure 60, the ADC needs a stabilization time of t before it starts STAB converting accurately. After the start of the ADC conversion and after 15 clock cycles, the EOC flag is set and the 16-bit ADC data register contains the result of the conversion. Figure 60. -
Page 337: Scan Mode
RM0430 Analog-to-digital converter (ADC) Table 75. Analog watchdog channel selection ADC_CR1 register control bits (x = don’t care) Channels guarded by the analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None All injected channels All regular channels All regular and injected channels Single injected channel Single... -
Page 338: Discontinuous Mode
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously. Figure 62. Injected conversion latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F413/423 datasheets. 13.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. -
Page 339: Data Alignment
RM0430 Analog-to-digital converter (ADC) Example: • n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 • 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion. • 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion •... -
Page 340: Channel-Wise Programmable Sampling Time
Analog-to-digital converter (ADC) RM0430 Figure 63. Right alignment of 12-bit data Figure 64. Left alignment of 12-bit data Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in Figure Figure 65. -
Page 341: Conversion On External Trigger And Trigger Polarity
RM0430 Analog-to-digital converter (ADC) 13.6 Conversion on external trigger and trigger polarity Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from “0b00”, then external events are able to trigger a conversion with the selected polarity. -
Page 342: Data Management
Analog-to-digital converter (ADC) RM0430 13.8 Data management 13.8.1 Using the DMA Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC_DR register. -
Page 343: Conversions Without Dma And Without Overrun Detection
RM0430 Analog-to-digital converter (ADC) 13.8.3 Conversions without DMA and without overrun detection It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). For that, the DMA must be disabled (DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). -
Page 344: Battery Charge Monitoring
Analog-to-digital converter (ADC) RM0430 The temperature sensor output voltage changes linearly with temperature. The offset of this linear function depends on each chip due to process variation (up to 45 °C from one chip to another). The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. -
Page 345: Adc Registers
RM0430 Analog-to-digital converter (ADC) 13.12 ADC registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers must be written at word level (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 13.12.1 ADC status register (ADC_SR) Address offset: 0x00... -
Page 346: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0430 13.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. OVRIE AWDEN JAWDEN Res. Res. Res. Res. Res. Res. DISCNUM[2:0] JDISCEN DISCEN JAUTO AWDSGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Bits 31:27 Reserved, must be kept at reset value. - Page 347 RM0430 Analog-to-digital converter (ADC) Bit 11 DISCEN: Discontinuous mode on regular channels This bit is set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion.
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Page 348: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0430 13.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 JSWSTAR Res. SWSTART EXTEN EXTSEL[3:0] Res. JEXTEN JEXTSEL[3:0] Res. Res. Res. Res. ALIGN EOCS Res. Res. Res. Res. Res. Res. CONT ADON Bit 31 Reserved, must be kept at reset value. Bit 30 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as the conversion starts. -
Page 349: Adc Sample Time Register 1 (Adc_Smpr1)
RM0430 Analog-to-digital converter (ADC) Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 63 Figure 0: Right alignment 1: Left alignment Bit 10 EOCS: End of conversion selection This bit is set and cleared by software. 0: The EOC bit is set at the end of each sequence of regular conversions. -
Page 350: Adc Sample Time Register 2 (Adc_Smpr2)
Analog-to-digital converter (ADC) RM0430 Bits 31: 27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: 000: 3 cycles 001: 15 cycles 010: 28 cycles... -
Page 351: Adc Watchdog Higher Threshold Register (Adc_Htr)
RM0430 Analog-to-digital converter (ADC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers. -
Page 352: Adc Regular Sequence Register 1 (Adc_Sqr1)
Analog-to-digital converter (ADC) RM0430 13.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. L[3:0] SQ16[4:1] SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. -
Page 353: Adc Regular Sequence Register 3 (Adc_Sqr3)
RM0430 Analog-to-digital converter (ADC) Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence 13.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. SQ6[4:0] SQ5[4:0] SQ4[4:1] SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0]... -
Page 354: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0430 13.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JL[1:0] JSQ4[4:1] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. -
Page 355: Adc Regular Data Register (Adc_Dr)
RM0430 Analog-to-digital converter (ADC) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only. They contain the conversion result from injected channel x. The data are left -or right-aligned as shown in Figure 63 Figure 13.12.14 ADC regular data register (ADC_DR) -
Page 356: Adc Common Control Register (Adc_Ccr)
Analog-to-digital converter (ADC) RM0430 Bit 2 JEOC1: Injected channel end of conversion of ADC1 This bit is a copy of the JEOC bit in the ADC1_SR register. Bit 1 EOC1: End of conversion of ADC1 This bit is a copy of the EOC bit in the ADC1_SR register. Bit 0 AWD1: Analog watchdog flag of ADC1 This bit is a copy of the AWD bit in the ADC1_SR register. - Page 357 RM0430 Analog-to-digital converter (ADC) Table 78. ADC register map and reset values (continued) Offset Register DISC ADC_CR1 AWDCH[4:0] NUM [2:0] 0x04 Reset value JEXTSEL ADC_CR2 EXTSEL [3:0] [3:0] 0x08 Reset value ADC_SMPR1 Sample time bits SMPx_x 0x0C Reset value ADC_SMPR2 Sample time bits SMPx_x 0x10 Reset value...
- Page 358 Analog-to-digital converter (ADC) RM0430 Table 78. ADC register map and reset values (continued) Offset Register ADC_DR Regular DATA[15:0] 0x4C Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. 358/1284 DocID029473 Rev 3...
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Page 359: Digital-To-Analog Converter (Dac)
RM0430 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 14.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. -
Page 360: Table 79. Dac Pins
Digital-to-analog converter (DAC) RM0430 Figure 67. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex... -
Page 361: Dac Functional Description
RM0430 Digital-to-analog converter (DAC) 14.3 DAC functional description 14.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only. -
Page 362: Dac Conversion
Digital-to-analog converter (DAC) RM0430 Figure 68. Data registers in single DAC channel mode • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –... -
Page 363: Dac Output Voltage
RM0430 Digital-to-analog converter (DAC) When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time t that depends on the power supply voltage and the SETTLING analog output load. Figure 70. Timing diagram for conversion with trigger disabled TEN = 0 14.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V... -
Page 364: Dma Request
Digital-to-analog converter (DAC) RM0430 If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. -
Page 365: Triangle-Wave Generation
RM0430 Digital-to-analog converter (DAC) Figure 71. DAC LFSR register calculation algorithm The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. -
Page 366: Dual Dac Channel Conversion
Digital-to-analog converter (DAC) RM0430 It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 73. DAC triangle wave generation Figure 74. DAC conversion (SW trigger enabled) with triangle wave generation Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. -
Page 367: Independent Trigger Without Wave Generation
RM0430 Digital-to-analog converter (DAC) 14.4.1 Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 368: Independent Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0430 14.4.4 Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 369: Simultaneous Trigger Without Wave Generation
RM0430 Digital-to-analog converter (DAC) 14.4.7 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 370: Simultaneous Trigger With Single Triangle Generation
Digital-to-analog converter (DAC) RM0430 14.4.10 Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •... -
Page 371: Dac Registers
RM0430 Digital-to-analog converter (DAC) 14.5 DAC registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 14.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU... - Page 372 Digital-to-analog converter (DAC) RM0430 Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 8 TRGO event 010: Timer 7 TRGO event 011: 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9...
- Page 373 RM0430 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
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Page 374: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC) RM0430 14.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved SWTRIG2 SWTRIG1 Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2... - Page 375 RM0430 Digital-to-analog converter (DAC) 14.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
- Page 376 Digital-to-analog converter (DAC) RM0430 14.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
- Page 377 RM0430 Digital-to-analog converter (DAC) 14.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
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Page 378: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC) RM0430 14.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. -
Page 379: Dac Status Register (Dac_Sr)
RM0430 Digital-to-analog converter (DAC) 14.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 DMAUDR2 Reserved Reserved rc_w1 DMAUDR1 Reserved Reserved rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). - Page 380 Digital-to-analog converter (DAC) RM0430 Table 81. DAC register map (continued) Offset Register DAC_ 0x18 Reserved DACC2DHR[11:0] Reserved DHR12L2 DAC_ 0x1C Reserved DACC2DHR[7:0] DHR8R2 DAC_ 0x20 Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] DHR12RD DAC_ 0x24 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved DHR12LD DAC_ 0x28 Reserved DACC2DHR[7:0] DACC1DHR[7:0] DHR8RD...
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Page 381: Digital Filter For Sigma Delta Modulators (Dfsdm)
RM0430 Digital filter for sigma delta modulators (DFSDM) Digital filter for sigma delta modulators (DFSDM) 15.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution. -
Page 382: Dfsdm Main Features
Digital filter for sigma delta modulators (DFSDM) RM0430 15.2 DFSDM main features • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) •... -
Page 383: Dfsdm Implementation
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.3 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 82. DFSDMx implementation DFSDM features DFSDM1 DFSDM2 Number of channels Number of filters Input from internal ADC Supported trigger sources Pulses skipper ID registers support 1. -
Page 384: Dfsdm Functional Description
Digital filter for sigma delta modulators (DFSDM) RM0430 15.4 DFSDM functional description 15.4.1 DFSDM block diagram Figure 75. Single DFSDM block diagram 384/1284 DocID029473 Rev 3... -
Page 385: Dfsdm Pins And Internal Signals
RM0430 Digital filter for sigma delta modulators (DFSDM) 1. This example shows 4 DFSDM filters and 8 input channels (max. configuration). 15.4.2 DFSDM pins and internal signals Table 83. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply. Power supply Digital ground power supply. -
Page 386: Dfsdm Reset And Clocks
Digital filter for sigma delta modulators (DFSDM) RM0430 Table 86. DFSDM2 triggers connection Trigger name Trigger source dfsdm_jtrg0 TIM1_TRGO3 dfsdm_jtrg1 TIM3_TRGO3 dfsdm_jtrg2 TIM8_TRGO4 dfsdm_jtrg3 TIM10_OC1 dfsdm_jtrg4 TIM2_TRGO2 dfsdm_jtrg5 TIM4_TRGO4 dfsdm_jtrg6 TIM11_OC1 dfsdm_jtrg7 TIM6_TRGO2 dfsdm_jtrg8 TIM7_TRGO2 dfsdm_jtrg9 EXTI11 dfsdm_jtrg10 EXTI15 Table 87. DFSDM break connection Break name Break destination dfsdm_break[0]... -
Page 387: Serial Channel Transceivers
RM0430 Digital filter for sigma delta modulators (DFSDM) DFSDM clocks The internal DFSDM clock f , which is used to drive the channel transceivers, DFSDMCLK digital processing blocks (digital filter, integrator) and next additional blocks (analog watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK (max. -
Page 388: Figure 76. Input Channel Pins Redirection
Digital filter for sigma delta modulators (DFSDM) RM0430 Figure 76. Input channel pins redirection Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register). - Page 389 RM0430 Digital filter for sigma delta modulators (DFSDM) SPI data input format operation In SPI format, the data stream is sent in serial format through data and clock signals. Data signal is always provided from DATINy pin. A clock signal can be provided externally from CKINy pin or internally from a signal derived from the CKOUT signal source.
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Page 390: Figure 77. Channel Transceiver Timing Diagrams
Digital filter for sigma delta modulators (DFSDM) RM0430 Figure 77. Channel transceiver timing diagrams 390/1284 DocID029473 Rev 3... -
Page 391: Figure 78. Clock Absence Timing Diagram For Spi
RM0430 Digital filter for sigma delta modulators (DFSDM) Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register. -
Page 392: Figure 79. Clock Absence Timing Diagram For Manchester Coding
Digital filter for sigma delta modulators (DFSDM) RM0430 The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register). - Page 393 RM0430 Digital filter for sigma delta modulators (DFSDM) Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:...
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Page 394: Figure 80. First Conversion For Manchester Coding (Manchester Synchronization)
Digital filter for sigma delta modulators (DFSDM) RM0430 Figure 80. First conversion for Manchester coding (Manchester synchronization) External serial clock frequency measurement The measuring of a channel serial clock input frequency provides a real data rate from an external Σ∆ modulator, which is important for application purposes. An external serial clock input frequency can be measured by a timer counting DFSDM clocks (f ) during one conversion duration. - Page 395 RM0430 Digital filter for sigma delta modulators (DFSDM) Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1):...
- Page 396 Digital filter for sigma delta modulators (DFSDM) RM0430 the final output sample (and next samples) from filter will be calculated from later input data. This final sample then looks a bit in forward - because it is calculated from newer input samples than the “non-skipped”...
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Page 397: Figure 81. Multi-Channel Delay Block For Pulse Skipping
RM0430 Digital filter for sigma delta modulators (DFSDM) Figure 81. Multi-channel delay block for pulse skipping DocID029473 Rev 3 397/1284... -
Page 398: Figure 82. Pulses Skipper Operation
Digital filter for sigma delta modulators (DFSDM) RM0430 The DFSDM shall be configured as follow: • CHINSEL must be set to 0 for all channels (channel data are taken from pins of the same channel) • SPICKSEL must be set to 0 for all channels (in order to select external CKINy as input clock) The TIM3 and TIM4 shall be configured as follow: •... -
Page 399: Table 88. Demultiplexers (Dm[6:1]) Operation
RM0430 Digital filter for sigma delta modulators (DFSDM) Table 88. Demultiplexers (DM[6:1]) operation Control Output 0 Output 1 input input Table 89. Use-cases examples for beamforming applications Use cases Multiplexer/ gate on schematic Speech recognition_1 OFF OFF OFF ON x x x x x x x x x x 0 0 x x x x x 0 0 Beamforming4_ OFF ON ON OFF 1 1 0 0 0 0 x x 1 1 1 0 x x x x x 0 1... -
Page 400: Configuring The Input Serial Interface
Digital filter for sigma delta modulators (DFSDM) RM0430 15.4.5 Configuring the input serial interface The following parameters must be configured for the input serial interface: • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in DFSDM_CH0CFGR1 register. - Page 401 RM0430 Digital filter for sigma delta modulators (DFSDM) address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading.
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Page 402: Channel Selection
Digital filter for sigma delta modulators (DFSDM) RM0430 Figure 83. DFSDM_CHyDATINR registers operation modes and assignment The write into DFSDM_CHyDATINR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y). -
Page 403: Digital Filter Configuration
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.4.8 Digital filter configuration DFSDM contains a Sinc type digital filter implementation. This Sinc filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sinc digital filter is configurable in order to reach the required output data rates and required output data resolution. -
Page 404: Integrator Unit
Digital filter for sigma delta modulators (DFSDM) RM0430 Table 90. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x +/- x +/- 2x +/- x +/- x +/- x +/- 4 +/- 16... - Page 405 RM0430 Digital filter for sigma delta modulators (DFSDM) Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0).
- Page 406 Digital filter for sigma delta modulators (DFSDM) RM0430 AWHTF[7:0], AWLTF[7:0] of DFSDM_FLTxAWSR register). Each channel request is executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8 DFSDM clock cycles (if AWDCH[7:0] = 0xFF). Because the maximum input channel sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog feature at this input clock speed.
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Page 407: Short-Circuit Detector
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.4.11 Short-circuit detector The purpose of a short-circuit detector is to signalize with a very fast response time if an analog signal reached saturated values (out of full scale ranges) and remained on this value given time. -
Page 408: Data Unit Block
Digital filter for sigma delta modulators (DFSDM) RM0430 15.4.13 Data unit block The data unit block is the last block of the whole processing path: External Σ∆ modulators - Serial transceivers - Sinc filter - Integrator - Data unit block. The output data rate depends on the serial data stream rate, and filter and integrator settings. -
Page 409: Signed Data Format
RM0430 Digital filter for sigma delta modulators (DFSDM) Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate ) must be limited to be able to read all output data: DATAIN_RATE ≤ f DATAIN_RATE where f is the bus frequency to which the DFSDM peripheral is connected. -
Page 410: Continuous And Fast Continuous Modes
Digital filter for sigma delta modulators (DFSDM) RM0430 already been issued but not yet completed. A regular conversion can be pending if it was interrupted by an injected conversion or if it was started while an injected conversion was in progress. -
Page 411: Power Optimization In Run Mode
RM0430 Digital filter for sigma delta modulators (DFSDM) An injected conversion cannot be launched if another injected conversion is pending or already in progress: any request to launch an injected conversion (either by JSWSTART or by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register). Similarly, a regular conversion cannot be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored as long as bit RCIP is ‘1’... -
Page 412: Table 92. Dfsdm Interrupt Requests
Digital filter for sigma delta modulators (DFSDM) RM0430 – enabled by JOVRIE bit in DFSDM_FLTxCR2 register – indicated in JOVRF bit in DFSDM_FLTxISR register – cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register • Data overrun interrupt for regular conversions: –... -
Page 413: Dfsdm Dma Transfer
RM0430 Digital filter for sigma delta modulators (DFSDM) Table 92. DFSDM interrupt requests (continued) Event/Interrupt clearing Interrupt enable Interrupt event Event flag method control bit Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE AWDF, writing CLRAWHTF[7:0] = 1 AWDIE, Analog watchdog AWHTF[7:0], writing CLRAWLTF[7:0] = 1... - Page 414 Digital filter for sigma delta modulators (DFSDM) RM0430 Bit 31 DFSDMEN: Global enable for DFSDM interface 0: DFSDM interface disabled 1: DFSDM interface enabled If DFSDM interface is enabled, then it is started to operate according to enabled y channels and enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
- Page 415 RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y 0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected. 1: Reserved 2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
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Page 416: Dfsdm_Chyawscdr) (Y=0..7)
Digital filter for sigma delta modulators (DFSDM) RM0430 15.7.2 DFSDM channel configuration y register (DFSDM_CHyCFGR2) (y=0..7) This register specifies the parameters used by channel y (y = 0..7). Address offset: 0x04 + 0x20 * y Reset value: 0x0000 0000 OFFSET[23:8] OFFSET[7:0] DTRBS[4:0] Res. - Page 417 RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:24 Reserved, must be kept at reset value. Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type FOSR...
- Page 418 Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 WDATA[15:0]: Input channel y watchdog data Data converted by the analog watchdog filter for input channel y. This data is continuously converted (no trigger) for this channel, with a limited resolution (OSR=1...32/sinc order = 1...3).
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Page 419: Dfsdm Filter X Module Registers (X=0..3)
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8 DFSDM filter x module registers (x=0..3) 15.8.1 DFSDM control register 1 (DFSDM_FLTxCR1) Address offset: 0x100 + 0x80 * x, x = 0...3 Reset value: 0x0000 0000 RDMA RCON Res. FAST Res. Res. - Page 420 Digital filter for sigma delta modulators (DFSDM) RM0430 Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
- Page 421 RM0430 Digital filter for sigma delta modulators (DFSDM) DFSDM2_FLT0 DFSDM2_FLT1 DFSDM2_FLT2 DFSDM2_FLT3 0x00 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0 dfsdm_jtrg0 0x01 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1 dfsdm_jtrg1 0x02 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2 dfsdm_jtrg2 0x03 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg3 dfsdm_jtrg4 0x04 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg5 dfsdm_jtrg6 0x05 dfsdm_jtrg7 dfsdm_jtrg7 dfsdm_jtrg8 dfsdm_jtrg8 0x06...
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Page 422: Dfsdm Control Register 2 (Dfsdm_Fltxcr2)
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8.2 DFSDM control register 2 (DFSDM_FLTxCR2) Address offset: 0x104 + 0x80 * x, x = 0...3 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. AWDCH[7:0] CKAB ROVR JOVRI REOC JEOCI EXCH[7:0]... -
Page 423: Dfsdm Interrupt And Status Register (Dfsdm_Fltxisr)
RM0430 Digital filter for sigma delta modulators (DFSDM) Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt is disabled 1: Injected data overrun interrupt is enabled Please see the explanation of JOVRF in DFSDM_FLTxISR. Bit 1 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt is disabled 1: Regular end of conversion interrupt is enabled Please see the explanation of REOCF in DFSDM_FLTxISR. - Page 424 Digital filter for sigma delta modulators (DFSDM) RM0430 Bit 14 RCIP: Regular conversion in progress status 0: No request to convert the regular channel has been issued 1: The conversion of the regular channel is in progress or a request for a regular conversion is pending A request to start a regular conversion is ignored when RCIP=1.
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Page 425: Dfsdm Interrupt Flag Clear Register (Dfsdm_Fltxicr)
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.4 DFSDM interrupt flag clear register (DFSDM_FLTxICR) Address offset: 0x10C + 0x80 * x, x = 0...3 Reset value: 0x0000 0000 CLRSCDF[7:0] CLRCKABF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1... -
Page 426: Dfsdm Filter Control Register (Dfsdm_Fltxfcr)
Digital filter for sigma delta modulators (DFSDM) RM0430 15.8.5 DFSDM injected channel group selection register (DFSDM_FLTxJCHGR) Address offset: 0x110 + 0x80 * x, x = 0...3 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 427: Dfsdm Data Register For Injected Group (Dfsdm_Fltxjdatar)
RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type 4: Sinc filter type 5: Sinc filter type 6-7: Reserved FOSR ⎛... - Page 428 Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value.
- Page 429 RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.9 DFSDM analog watchdog high threshold register (DFSDM_FLTxAWHTR) Address offset: 0x120 + 0x80 * x, x = 0...3 Reset value: 0x0000 0000 AWHT[23:8] AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0] Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog.
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Page 430: Dfsdm Analog Watchdog Status Register (Dfsdm_Fltxawsr)
Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution). - Page 431 RM0430 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDM_FLTxAWSR register Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’...
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Page 432: Dfsdm Conversion Timer Register (Dfsdm_Fltxcnvtimr)
Digital filter for sigma delta modulators (DFSDM) RM0430 Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:3 Reserved, must be kept at reset value. -
Page 433: Dfsdm Register Map
RM0430 Digital filter for sigma delta modulators (DFSDM) 15.8.16 DFSDM register map The following table summarizes the DFSDM registers. Table 93. DFSDM register map and reset values Offset Register DFSDM_ CKOUTDIV[7:0] CH0CFGR1 0x00 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH0CFGR2 0x04 reset value DFSDM_ AWFOSR[4:0]... - Page 434 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ CH2CFGR1 0x40 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH2CFGR2 0x44 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH2AWSCDR 0x48 reset value DFSDM_ WDATA[15:0] CH2WDATR 0x4C...
- Page 435 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ OFFSET[23:0] DTRBS[4:0] CH4CFGR2 0x84 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH4AWSCDR 0x88 reset value DFSDM_ WDATA[15:0] CH4WDATR 0x8C reset value DFSDM_ INDAT1[15:0] INDAT0[15:0]...
- Page 436 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH6AWSCDR 0xC8 reset value DFSDM_ WDATA[15:0] CH6WDATR 0xCC reset value DFSDM_ INDAT1[15:0] INDAT0[15:0] CH6DATINR 0xD0 reset value 0xD4 - Reserved 0xDC...
- Page 437 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ CLRSCDF[7:0] CLRCKABF[7:0] FLT0ICR 0x10C reset value DFSDM_ JCHG[7:0] FLT0JCHGR 0x110 reset value DFSDM_ FOSR[9:0] IOSR[7:0] FLT0FCR 0x114 reset value DFSDM_ JDATA[23:0] FLT0JDATAR 0x118...
- Page 438 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ RCH[2:0] JEXTSEL[4:0] FLT1CR1 0x180 reset value DFSDM_ AWDCH[7:0] EXCH[7:0] FLT1CR2 0x184 reset value DFSDM_ FLT1ISR 0x188 reset value DFSDM_ FLT1ICR 0x18C reset value JCHG[7:0]...
- Page 439 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ EXMAX[23:0] FLT1EXMAX 0x1B0 reset value DFSDM_ EXMIN[23:0] FLT1EXMIN 0x1B4 reset value DFSDM_ CNVCNT[27:0] FLT1CNVTIMR 0x1B8 reset value 0x1BC - Reserved 0x1FC DFSDM_ RCH[2:0]...
- Page 440 Digital filter for sigma delta modulators (DFSDM) RM0430 Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ RDATA RDATA[23:0] FLT2RDATAR CH[2:0] 0x21C reset value DFSDM_ AWHT[23:0] BKAWH[3:0] FLT2AWHTR 0x220 reset value DFSDM_ AWLT[23:0] BKAWL[3:0] FLT2AWLTR 0x224 reset value DFSDM_ AWHTF[7:0] AWLTF[7:0]...
- Page 441 RM0430 Digital filter for sigma delta modulators (DFSDM) Table 93. DFSDM register map and reset values (continued) Offset Register DFSDM_ FOSR[9:0] IOSR[7:0] FLT3FCR 0x294 reset value DFSDM_ JDATA[23:0] FLT3JDATAR 0x298 reset value DFSDM_ RDATA RDATA[23:0] FLT3RDATAR CH[2:0] 0x29C reset value DFSDM_ AWHT[23:0] BKAWH[3:0]...
- Page 442 True Random Number Generator (RNG) RM0430 True Random Number Generator (RNG) 16.1 Introduction The RNG is a true random number generator that continuously provides 32-bit entropy samples, based on an analog noise source. It can be used by the application as a live entropy source to build a NIST compliant Deterministic Random Bit Generator (DRBG).
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Page 443: Rng Internal Signals
RM0430 True Random Number Generator (RNG) Figure 85. RNG block diagram 16.3.2 RNG internal signals Table 94 describes a list of useful-to-know internal signals available at the RNG level, not at the STM32 product level (on pads). Table 94. RNG internal input/output signals Signal name Signal type Description... -
Page 444: Figure 86. Entropy Source Model
True Random Number Generator (RNG) RM0430 Figure 86. Entropy source model The main components of the RNG are: • A source of physical randomness (analog noise source) • A digitization stage for this analog noise source • A stage delivering post-processed noise source (raw data) •... - Page 445 RM0430 True Random Number Generator (RNG) Post processing The sample values obtained from a true random noise source consist of 2-bit bitstrings. Because this noise source output is biased, the RNG implements a post-processing component that reduces that bias to a tolerable level. The RNG post-processing consists of two stages, applied to each noise source bits: •...
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Page 446: Rng Initialization
True Random Number Generator (RNG) RM0430 16.3.4 RNG initialization When a hardware reset occurs the following chain of events occurs: The analog noise source is enabled, and logic starts sampling the analog output after four RNG clock cycles, filling LFSR shift register and associated 16-bit post-processing shift register. - Page 447 RM0430 True Random Number Generator (RNG) Caution: When the CEC bit in the RNG_CR register is set to “1”, the RNG clock frequency must be higher than AHB clock frequency divided by 16, otherwise the clock checker will flag a clock error (CECS or CEIS in the RNG_SR register) and the RNG will stop producing random numbers.
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Page 448: Rng Processing Time
True Random Number Generator (RNG) RM0430 Table 95. RNG interrupt requests Interrupt event Event flag Enable control bit Data ready flag DRDY Seed error flag SEIS Clock error flag CEIS The user can enable or disable the above interrupt sources individually by changing the mask bits or the general interrupt control bit IE in the RNG_CR register. -
Page 449: Rng Registers
RM0430 True Random Number Generator (RNG) 16.8 RNG registers The RNG is associated with a control register, a data register and a status register. 16.8.1 RNG control register (RNG_CR) Address offset: 0x000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. -
Page 450: Rng Data Register (Rng_Dr)
True Random Number Generator (RNG) RM0430 Bits 31:7 Reserved, must be kept at reset value Bit 6 SEIS: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to ‘0’. 0: No faulty sequence detected 1: At least one faulty sequence has been detected. -
Page 451: Rng Register Map
RM0430 True Random Number Generator (RNG) 16.8.4 RNG register map Table 96 gives the RNG register map and reset values. Table 96. RNG register map and reset map Register size Register name Offset reset value RNG_CR 0x000 Reset value RNG_SR 0x004 Reset value 0 0 0... -
Page 452: Tim1&Tim8 Introduction
Advanced-control timers (TIM1&TIM8) RM0430 Advanced-control timers (TIM1&TIM8) 17.1 TIM1&TIM8 introduction The advanced-control timer (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse length of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). -
Page 453: Figure 87. Advanced-Control Timer Block Diagram
RM0430 Advanced-control timers (TIM1&TIM8) Figure 87. Advanced-control timer block diagram DocID029473 Rev 3 453/1284... -
Page 454: Tim1&Tim8 Functional Description
Advanced-control timers (TIM1&TIM8) RM0430 17.3 TIM1&TIM8 functional description 17.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. -
Page 455: Figure 88. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0430 Advanced-control timers (TIM1&TIM8) Figure 88. Counter timing diagram with prescaler division change from 1 to 2 Figure 89. Counter timing diagram with prescaler division change from 1 to 4 DocID029473 Rev 3 455/1284... -
Page 456: Counter Modes
Advanced-control timers (TIM1&TIM8) RM0430 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1). -
Page 457: Figure 91. Counter Timing Diagram, Internal Clock Divided By 2
RM0430 Advanced-control timers (TIM1&TIM8) Figure 91. Counter timing diagram, internal clock divided by 2 Figure 92. Counter timing diagram, internal clock divided by 4 Figure 93. Counter timing diagram, internal clock divided by N DocID029473 Rev 3 457/1284... -
Page 458: Figure 94. Counter Timing Diagram, Update Event When Arpe
Advanced-control timers (TIM1&TIM8) RM0430 Figure 94. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 95. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 458/1284 DocID029473 Rev 3... - Page 459 RM0430 Advanced-control timers (TIM1&TIM8) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).
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Page 460: Figure 96. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0430 Figure 96. Counter timing diagram, internal clock divided by 1 Figure 97. Counter timing diagram, internal clock divided by 2 460/1284 DocID029473 Rev 3... -
Page 461: Figure 98. Counter Timing Diagram, Internal Clock Divided By 4
RM0430 Advanced-control timers (TIM1&TIM8) Figure 98. Counter timing diagram, internal clock divided by 4 Figure 99. Counter timing diagram, internal clock divided by N DocID029473 Rev 3 461/1284... -
Page 462: Figure 100. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
Advanced-control timers (TIM1&TIM8) RM0430 Figure 100. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event. -
Page 463: Figure 101. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0430 Advanced-control timers (TIM1&TIM8) DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •... -
Page 464: Figure 103. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
Advanced-control timers (TIM1&TIM8) RM0430 Figure 103. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 104. Counter timing diagram, internal clock divided by N 464/1284 DocID029473 Rev 3... -
Page 465: Repetition Counter
RM0430 Advanced-control timers (TIM1&TIM8) Figure 105. Counter timing diagram, update event with ARPE=1 (counter underflow) Figure 106. Counter timing diagram, update event with ARPE=1 (counter overflow) 17.3.3 Repetition counter Section 17.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. - Page 466 Advanced-control timers (TIM1&TIM8) RM0430 The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
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Page 467: Figure 107. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0430 Advanced-control timers (TIM1&TIM8) Figure 107. Update rate examples depending on mode and TIMx_RCR register settings DocID029473 Rev 3 467/1284... -
Page 468: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0430 17.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2. -
Page 469: Figure 109. Ti2 External Clock Connection Example
RM0430 Advanced-control timers (TIM1&TIM8) Figure 109. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. -
Page 470: Figure 110. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1&TIM8) RM0430 Figure 110. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 111 gives an overview of the external trigger input block. -
Page 471: Capture/Compare Channels
RM0430 Advanced-control timers (TIM1&TIM8) As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. -
Page 472: Figure 113. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1&TIM8) RM0430 Figure 113. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 114. Capture/compare channel 1 main circuit 472/1284 DocID029473 Rev 3... -
Page 473: Figure 115. Output Stage Of Capture/Compare Channel (Channels 1 To 3)
RM0430 Advanced-control timers (TIM1&TIM8) Figure 115. Output stage of capture/compare channel (channels 1 to 3) Figure 116. Output stage of capture/compare channel (channel 4) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. -
Page 474: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0430 17.3.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. -
Page 475: Pwm Input Mode
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.7 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •... -
Page 476: Output Compare Mode
Advanced-control timers (TIM1&TIM8) RM0430 To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) =>... -
Page 477: Pwm Mode
RM0430 Advanced-control timers (TIM1&TIM8) Figure 118. Output compare mode, toggle on OC1. 17.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. -
Page 478: Figure 119. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0430 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <... -
Page 479: Figure 120. Center-Aligned Pwm Waveforms (Arr=8)
RM0430 Advanced-control timers (TIM1&TIM8) Figure 120 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 120. -
Page 480: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0430 Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. -
Page 481: Figure 121. Complementary Output With Dead-Time Insertion
RM0430 Advanced-control timers (TIM1&TIM8) Figure 121. Complementary output with dead-time insertion. Figure 122. Dead-time waveforms with delay greater than the negative pulse. Figure 123. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. -
Page 482: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0430 are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. - Page 483 RM0430 Advanced-control timers (TIM1&TIM8) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
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Page 484: Figure 124. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0430 Figure 124. Output behavior in response to a break. 484/1284 DocID029473 Rev 3... -
Page 485: Clearing The Ocxref Signal On An External Event
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. -
Page 486: Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0430 17.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. -
Page 487: One-Pulse Mode
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. -
Page 488: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0430 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1). -
Page 489: Table 97. Counting Direction Versus Encoder Signals
RM0430 Advanced-control timers (TIM1&TIM8) configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. -
Page 490: Figure 128. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0430 Figure 128. Example of counter operation in encoder interface mode. Figure 129 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. -
Page 491: Timer Input Xor Function
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. -
Page 492: Figure 130. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0430 Figure 130 describes this example. Figure 130. Example of Hall sensor interface 492/1284 DocID029473 Rev 3... -
Page 493: Timx And External Trigger Synchronization
RM0430 Advanced-control timers (TIM1&TIM8) 17.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. -
Page 494: Figure 132. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0430 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 495: Figure 133. Control Circuit In Trigger Mode
RM0430 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). -
Page 496: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0430 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –... -
Page 497: Tim1&Tim8 Registers
RM0430 Advanced-control timers (TIM1&TIM8) 17.4 TIM1&TIM8 registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers must be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-word (16 bits) or words (32 bits). -
Page 498: Tim1&Tim8 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0430 Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. - Page 499 RM0430 Advanced-control timers (TIM1&TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
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Page 500: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0430 Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). - Page 501 RM0430 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
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Page 502: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. - Page 503 RM0430 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
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Page 504: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value. -
Page 505: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0430 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). - Page 506 Advanced-control timers (TIM1&TIM8) RM0430 Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output.
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Page 507: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 508 Advanced-control timers (TIM1&TIM8) RM0430 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 509 RM0430 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
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Page 510: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events... -
Page 511: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0430 Advanced-control timers (TIM1&TIM8) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4... - Page 512 Advanced-control timers (TIM1&TIM8) RM0430 Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description...
- Page 513 RM0430 Advanced-control timers (TIM1&TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
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Page 514: With Break Feature
Advanced-control timers (TIM1&TIM8) RM0430 Table 99. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the timer) the timer) OCxN=0, OCxN_EN=0 OCx=0, OCx_EN=0... -
Page 515: Tim1&Tim8 Counter (Timx_Cnt)
RM0430 Advanced-control timers (TIM1&TIM8) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers. 17.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 17.4.11... -
Page 516: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. -
Page 517: Tim1 Capture/Compare Register 2 (Timx_Ccr2)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.15 TIM1 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). -
Page 518: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1&TIM8) RM0430 17.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). - Page 519 RM0430 Advanced-control timers (TIM1&TIM8) Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
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Page 520: Tim1&Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1&TIM8) RM0430 Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>... -
Page 521: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0430 Advanced-control timers (TIM1&TIM8) 17.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the... -
Page 522: Tim1&Tim8 Register Map
Advanced-control timers (TIM1&TIM8) RM0430 17.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 100. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS... - Page 523 RM0430 Advanced-control timers (TIM1&TIM8) Table 100. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reset value TIMx_DCR DBL[4:0]...
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Page 524: Tim2 To Tim5 Introduction
General-purpose timers (TIM2 to TIM5) RM0430 General-purpose timers (TIM2 to TIM5) 18.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). -
Page 525: Tim2 To Tim5 Functional Description
RM0430 General-purpose timers (TIM2 to TIM5) Figure 135. General-purpose timer block diagram 18.3 TIM2 to TIM5 functional description 18.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. -
Page 526: Figure 136. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0430 The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. - Page 527 RM0430 General-purpose timers (TIM2 to TIM5) Figure 137. Counter timing diagram with prescaler division change from 1 to 4 18.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
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Page 528: Figure 138. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 138. Counter timing diagram, internal clock divided by 1 Figure 139. Counter timing diagram, internal clock divided by 2 Figure 140. Counter timing diagram, internal clock divided by 4 528/1284 DocID029473 Rev 3... -
Page 529: Figure 141. Counter Timing Diagram, Internal Clock Divided By N
RM0430 General-purpose timers (TIM2 to TIM5) Figure 141. Counter timing diagram, internal clock divided by N Figure 142. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) DocID029473 Rev 3 529/1284... - Page 530 General-purpose timers (TIM2 to TIM5) RM0430 Figure 143. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
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Page 531: Figure 144. Counter Timing Diagram, Internal Clock Divided By 1
RM0430 General-purpose timers (TIM2 to TIM5) Figure 144. Counter timing diagram, internal clock divided by 1 Figure 145. Counter timing diagram, internal clock divided by 2 Figure 146. Counter timing diagram, internal clock divided by 4 DocID029473 Rev 3 531/1284... -
Page 532: Figure 147. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0430 Figure 147. Counter timing diagram, internal clock divided by N Figure 148. Counter timing diagram, Update event Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –... -
Page 533: Figure 149. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0430 General-purpose timers (TIM2 to TIM5) In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. -
Page 534: Figure 150. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0430 Figure 150. Counter timing diagram, internal clock divided by 2 Figure 151. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 152. -
Page 535: Figure 153. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0430 General-purpose timers (TIM2 to TIM5) Figure 153. Counter timing diagram, Update event with ARPE=1 (counter underflow) Figure 154. Counter timing diagram, Update event with ARPE=1 (counter overflow) DocID029473 Rev 3 535/1284... - Page 536 General-purpose timers (TIM2 to TIM5) RM0430 18.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4 only.
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Page 537: Figure 156. Ti2 External Clock Connection Example
RM0430 General-purpose timers (TIM2 to TIM5) Figure 156. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. -
Page 538: Figure 157. Control Circuit In External Clock Mode 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 157. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 158 gives an overview of the external trigger input block. - Page 539 RM0430 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 159. Control circuit in external clock mode 2 18.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a...
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Page 540: Figure 160. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2 to TIM5) RM0430 Figure 160. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 161. - Page 541 RM0430 General-purpose timers (TIM2 to TIM5) Figure 162. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
- Page 542 General-purpose timers (TIM2 to TIM5) RM0430 new level have been detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
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Page 543: Forced Output Mode
RM0430 General-purpose timers (TIM2 to TIM5) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): •... - Page 544 General-purpose timers (TIM2 to TIM5) RM0430 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
- Page 545 RM0430 General-purpose timers (TIM2 to TIM5) Figure 164. Output compare mode, toggle on OC1 18.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
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Page 546: Figure 165. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0430 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 527. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. -
Page 547: Figure 166. Center-Aligned Pwm Waveforms (Arr=8)
RM0430 General-purpose timers (TIM2 to TIM5) Center-aligned mode (up/down counting) on page 532. Figure 166 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. - Page 548 General-purpose timers (TIM2 to TIM5) RM0430 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
- Page 549 RM0430 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
- Page 550 General-purpose timers (TIM2 to TIM5) RM0430 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
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Page 551: Table 101. Counting Direction Versus Encoder Signals
RM0430 General-purpose timers (TIM2 to TIM5) In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. -
Page 552: Figure 169. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0430 Figure 169. Example of counter operation in encoder interface mode Figure 170 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 170. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. - Page 553 RM0430 General-purpose timers (TIM2 to TIM5) 18.3.13 Timer input XOR function The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
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Page 554: Figure 172. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0430 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 555: Figure 173. Control Circuit In Trigger Mode
RM0430 General-purpose timers (TIM2 to TIM5) The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 173. Control circuit in trigger mode Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). - Page 556 General-purpose timers (TIM2 to TIM5) RM0430 Figure 174. Control circuit in external clock mode 2 + trigger mode 18.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
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Page 557: Figure 176. Gating Timer 2 With Oc1Ref Of Timer 1
RM0430 General-purpose timers (TIM2 to TIM5) For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 175. To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV. -
Page 558: Figure 177. Gating Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0430 you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. -
Page 559: Figure 178. Triggering Timer 2 With Update Of Timer 1
RM0430 General-purpose timers (TIM2 to TIM5) counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3). CK_CNT CK_INT • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). -
Page 560: Figure 179. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0430 Figure 179. Triggering timer 2 with Enable of timer 1 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 175 for connections. -
Page 561: Debug Mode
RM0430 General-purpose timers (TIM2 to TIM5) counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): • Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register). -
Page 562: Tim2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0430 18.4 TIM2 to TIM5 registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). - Page 563 RM0430 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
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Page 564: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) -
Page 565: Timx Slave Mode Control Register (Timx_Smcr)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable... -
Page 566: Table 102. Timx Internal Trigger Connections
General-purpose timers (TIM2 to TIM5) RM0430 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. -
Page 567: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. -
Page 568: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0430 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 18.4.5... - Page 569 RM0430 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
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Page 570: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. -
Page 571: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 572 General-purpose timers (TIM2 to TIM5) RM0430 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 573 RM0430 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
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Page 574: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode... -
Page 575: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0430 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3... -
Page 576: Table 103. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2 to TIM5) RM0430 Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. -
Page 577: Timx Counter (Timx_Cnt)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 18.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). -
Page 578: Timx Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[31:16] (depending on timers) CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). -
Page 579: Timx Capture/Compare Register 3 (Timx_Ccr3)
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 CCR3[31:16] (depending on timers) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). -
Page 580: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). -
Page 581: Tim2 Option Register (Tim2_Or)
RM0430 General-purpose timers (TIM2 to TIM5) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –... -
Page 582: Tim5 Option Register (Tim5_Or)
General-purpose timers (TIM2 to TIM5) RM0430 18.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP Res. Res. Res. Res. Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software. -
Page 583: Timx Register Map
RM0430 General-purpose timers (TIM2 to TIM5) 18.4.21 TIMx register map TIMx registers are mapped as described in the table below: Table 104. TIM2 to TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS... - Page 584 General-purpose timers (TIM2 to TIM5) RM0430 Table 104. TIM2 to TIM5 register map and reset values (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved CCR1[31:16]...
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Page 585: Tim9 To Tim14 Introduction
RM0430 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) 19.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM). -
Page 586: Tim10/Tim11 And Tim13/Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0430 Figure 181. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 Trigger controller ITR1 ITR2 TRGI Slave ITR3 Reset, Enable, Count mode TI1F_ED controller TI1FP1 TI2FP2 Auto-reload register Stop, Clear CK_PSC CK_CNT Prescaler COUNTER CC1I... -
Page 587: Figure 182. General-Purpose Timer Block Diagram (Tim10/11/13/14)
RM0430 General-purpose timers (TIM9 to TIM14) Figure 182. General-purpose timer block diagram (TIM10/11/13/14) DocID029473 Rev 3 587/1284... -
Page 588: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0430 19.3 TIM9 to TIM14 functional description 19.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. -
Page 589: Figure 183. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0430 General-purpose timers (TIM9 to TIM14) Figure 183. Counter timing diagram with prescaler division change from 1 to 2 Figure 184. Counter timing diagram with prescaler division change from 1 to 4 DocID029473 Rev 3 589/1284... - Page 590 General-purpose timers (TIM9 to TIM14) RM0430 19.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event.
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Page 591: Figure 186. Counter Timing Diagram, Internal Clock Divided By 2
RM0430 General-purpose timers (TIM9 to TIM14) Figure 186. Counter timing diagram, internal clock divided by 2 Figure 187. Counter timing diagram, internal clock divided by 4 Figure 188. Counter timing diagram, internal clock divided by N DocID029473 Rev 3 591/1284... -
Page 592: Figure 189. Counter Timing Diagram, Update Event When Arpe
General-purpose timers (TIM9 to TIM14) RM0430 Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 190. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 592/1284 DocID029473 Rev 3... - Page 593 RM0430 General-purpose timers (TIM9 to TIM14) 19.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer.
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Page 594: Figure 192. Ti2 External Clock Connection Example
General-purpose timers (TIM9 to TIM14) RM0430 Figure 192. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. - Page 595 RM0430 General-purpose timers (TIM9 to TIM14) 19.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 194 Figure 196 give an overview of one capture/compare channel.
- Page 596 General-purpose timers (TIM9 to TIM14) RM0430 Figure 195. Capture/compare channel 1 main circuit Figure 196. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
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Page 597: Pwm Input Mode (Only For Tim9/12)
RM0430 General-purpose timers (TIM9 to TIM14) cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. - Page 598 General-purpose timers (TIM9 to TIM14) RM0430 Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
- Page 599 RM0430 General-purpose timers (TIM9 to TIM14) 19.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
- Page 600 General-purpose timers (TIM9 to TIM14) RM0430 Figure 198. Output compare mode, toggle on OC1. 19.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
- Page 601 RM0430 General-purpose timers (TIM9 to TIM14) Figure 199. Edge-aligned PWM waveforms (ARR=8) 19.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
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Page 602: Figure 200. Example Of One Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 200. Example of one pulse mode. For example you may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin. DELAY Use TI2FP2 as trigger 1: Map TI2FP2 to TI2 by writing CC2S=’01’... -
Page 603: Tim9/12 External Trigger Synchronization
RM0430 General-purpose timers (TIM9 to TIM14) Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. -
Page 604: Figure 201. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0430 Figure 201. Control circuit in reset mode Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. -
Page 605: Figure 202. Control Circuit In Gated Mode
RM0430 General-purpose timers (TIM9 to TIM14) Figure 202. Control circuit in gated mode Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. -
Page 606: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0430 19.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 18.3.15: Timer synchronization for details. 19.3.13 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. - Page 607 RM0430 General-purpose timers (TIM9 to TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
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Page 608: Tim9/12 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.2 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. TS[2:0] Res. SMS[2:0] Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). -
Page 609: Tim9/12 Interrupt Enable Register (Timx_Dier)
RM0430 General-purpose timers (TIM9 to TIM14) Table 105. TIMx internal trigger connections Slave TIM ITR0 (TS = ‘000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ‘011’) TIM9 TIM2 TIM3 or LPTIM1 TIM10_OC TIM11_OC TIM12 TIM4 TIM5 TIM13_OC TIM14_OC 1. -
Page 610: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0430 19.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. Res. Res. Res. CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag... -
Page 611: Tim9/12 Event Generation Register (Timx_Egr)
RM0430 General-purpose timers (TIM9 to TIM14) Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. -
Page 612: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM9 to TIM14) RM0430 Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. - Page 613 RM0430 General-purpose timers (TIM9 to TIM14) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
- Page 614 General-purpose timers (TIM9 to TIM14) RM0430 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
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Page 615: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
RM0430 General-purpose timers (TIM9 to TIM14) 19.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value. -
Page 616: Tim9/12 Counter (Timx_Cnt)
General-purpose timers (TIM9 to TIM14) RM0430 Table 106. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers. -
Page 617: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
RM0430 General-purpose timers (TIM9 to TIM14) 19.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). -
Page 618: Tim9/12 Register Map
General-purpose timers (TIM9 to TIM14) RM0430 19.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: Table 107. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reset value TIMx_DIER 0x0C... - Page 619 RM0430 General-purpose timers (TIM9 to TIM14) Table 107. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reset value 0x3C to Reserved 0x4C Refer to Section 2.2.2 on page 56 for the register boundary addresses. DocID029473 Rev 3 619/1284...
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Page 620: Tim10/11/13/14 Registers
General-purpose timers (TIM9 to TIM14) RM0430 19.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 19.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00... -
Page 621: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1IE Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled... -
Page 622: Tim10/11/13/14 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0430 Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. -
Page 623: Tim10/11/13/14 Capture/Compare Mode Register
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 624 General-purpose timers (TIM9 to TIM14) RM0430 Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
- Page 625 RM0430 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
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Page 626: Table 108. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM9 to TIM14) RM0430 19.5.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP Res. CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. -
Page 627: Tim10/11/13/14 Counter (Timx_Cnt)
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). -
Page 628: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0430 19.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). -
Page 629: Tim10/11/13/14 Register Map
RM0430 General-purpose timers (TIM9 to TIM14) 19.5.12 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 109. TIM10/11/13/14 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reset value TIMx_SMCR 0x08 Reset value TIMx_DIER... - Page 630 General-purpose timers (TIM9 to TIM14) RM0430 Table 109. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reset value 0x38 to Reserved 0x4C TIMx_OR 0x50 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. 630/1284 DocID029473 Rev 3...
- Page 631 RM0430 Basic timers (TIM6/7) Basic timers (TIM6/7) 20.1 Introduction The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. 20.2 TIM6/7 main features Basic timer (TIM6/TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 •...
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Page 632: Tim6/7 Functional Description
Basic timers (TIM6/7) RM0430 20.3 TIM6/7 functional description 20.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. -
Page 633: Figure 205. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0430 Basic timers (TIM6/7) Figure 205. Counter timing diagram with prescaler division change from 1 to 2 Figure 206. Counter timing diagram with prescaler division change from 1 to 4 DocID029473 Rev 3 633/1284... -
Page 634: Counting Mode
Basic timers (TIM6/7) RM0430 20.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). -
Page 635: Figure 208. Counter Timing Diagram, Internal Clock Divided By 2
RM0430 Basic timers (TIM6/7) Figure 208. Counter timing diagram, internal clock divided by 2 Figure 209. Counter timing diagram, internal clock divided by 4 DocID029473 Rev 3 635/1284... -
Page 636: Figure 210. Counter Timing Diagram, Internal Clock Divided By N
Basic timers (TIM6/7) RM0430 Figure 210. Counter timing diagram, internal clock divided by N Figure 211. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) 636/1284 DocID029473 Rev 3... -
Page 637: Clock Source
RM0430 Basic timers (TIM6/7) Figure 212. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) 20.3.3 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). - Page 638 Basic timers (TIM6/7) RM0430 Figure 213. Control circuit in normal mode, internal clock divided by 1 20.3.4 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module.
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Page 639: Tim6/7 Registers
RM0430 Basic timers (TIM6/7) 20.4 TIM6/7 registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). -
Page 640: Tim6/7 Control Register 2 (Timx_Cr2)
Basic timers (TIM6/7) RM0430 20.4.2 TIM6/7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). -
Page 641: Tim6/7 Status Register (Timx_Sr)
RM0430 Basic timers (TIM6/7) 20.4.4 TIM6/7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. -
Page 642: Tim6/7 Prescaler (Timx_Psc)
Basic timers (TIM6/7) RM0430 20.4.7 TIM6/7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). -
Page 643: Tim6/7 Register Map
RM0430 Basic timers (TIM6/7) 20.4.9 TIM6/7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 110. TIM6 register map and reset values Offset Register TIMx_CR1 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value 0x08 Res. - Page 644 Configurable output: Pulse, PWM • Configurable I/O polarity • Encoder mode 21.3 LPTIM implementation Table 111 describes LPTIM implementation on STM32F413/423 devices. Table 111. STM32F413/423 LPTIM features LPTIM modes/features LPTIM1 Encoder mode 1. X = supported. 644/1284 DocID029473 Rev 3...
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Page 645: Lptim Functional Description
RM0430 Low-power timer (LPTIM) 21.4 LPTIM functional description 21.4.1 LPTIM block diagram Figure 214. Low-power timer block diagram 21.4.2 LPTIM input1 multiplexing Various inputs can be selected for LPTIM1 input 1 through the LPTMI option register (LPTIM1_OR). This input can either be connected to the pads selected by the LPTIM alternate function (AF1) or directly connected internally to PA4, PB9 pad or to TIM6/DAC trigger. -
Page 646: Lptim Reset And Clocks
Low-power timer (LPTIM) RM0430 21.4.3 LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be chosen among APB, LSI, LSE or HSI sources through the Clock Tree controller (RCC). -
Page 647: Prescaler
RM0430 Low-power timer (LPTIM) Figure 215. Glitch filter timing diagram Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches. -
Page 648: Operating Mode
Low-power timer (LPTIM) RM0430 The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled). -
Page 649: And Set-Once Mode Activated (Wave Bit Is Set)
RM0430 Low-power timer (LPTIM) Figure 217. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one shot counting. To enable the continuous counting, the CNTSTRT bit must be set. -
Page 650: Timeout Function
Low-power timer (LPTIM) RM0430 21.4.8 Timeout function The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart. -
Page 651: Register Update
RM0430 Low-power timer (LPTIM) Figure 219. Waveform generation 21.4.10 Register update The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started. The PRELOAD bit controls how the LPTIM_ARR and the LPTIM_CMP registers are updated: •... -
Page 652: Counter Mode
Low-power timer (LPTIM) RM0430 21.4.11 Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits. -
Page 653: Encoder Mode
RM0430 Low-power timer (LPTIM) 21.4.13 Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to 0 depending on the direction). -
Page 654: Lptim Interrupts
Low-power timer (LPTIM) RM0430 Figure 220. Encoder mode counting sequence 21.5 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIM_IER register: • Compare match • Auto-reload match (whatever the direction if encoder mode) •... -
Page 655: Lptim Registers
RM0430 Low-power timer (LPTIM) 21.6 LPTIM registers 21.6.1 LPTIM interrupt and status register (LPTIM_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 656: Lptim Interrupt Clear Register (Lptim_Icr)
Low-power timer (LPTIM) RM0430 21.6.2 LPTIM interrupt clear register (LPTIM_ICR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN ARRO CMPO EXTTR ARRM CMPM Res. Res. -
Page 657: Lptim Interrupt Enable Register (Lptim_Ier)
RM0430 Low-power timer (LPTIM) 21.6.3 LPTIM interrupt enable register (LPTIM_IER) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNI ARRO CMPO EXTTR ARRMI CMPMI Res. Res. -
Page 658: Lptim Configuration Register (Lptim_Cfgr)
Low-power timer (LPTIM) RM0430 21.6.4 LPTIM configuration register (LPTIM_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 COUNT Res. Res. Res. Res. Res. Res. Res. PRELOAD WAVPOL WAVE TIMOUT TRIGEN Res. MODE TRIGSEL Res. PRESC Res. TRGFLT Res. CKFLT CKPOL CKSEL Bits 31:25 Reserved, must be kept at reset value. - Page 659 RM0430 Low-power timer (LPTIM) Bits 15:13 TRIGSEL: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: PB6 or PC3 input on AF1 001: RTC alarm A output signal 010: RTC alarm B output signal 011: RTC tamper output signal 100: TIM1 trigger output (4) output signal...
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Page 660: Table 114. Lptim External Trigger Connection
Low-power timer (LPTIM) RM0430 Bits 4:3 CKFLT: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is... -
Page 661: Lptim Control Register (Lptim_Cr)
RM0430 Low-power timer (LPTIM) 21.6.5 LPTIM control register (LPTIM_CR) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 662: Lptim Compare Register (Lptim_Cmp)
Low-power timer (LPTIM) RM0430 21.6.6 LPTIM compare register (LPTIM_CMP) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CMP[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP: Compare value CMP is the compare value used by the LPTIM. -
Page 663: Lptim Counter Register (Lptim_Cnt)
RM0430 Low-power timer (LPTIM) 21.6.8 LPTIM counter register (LPTIM_CNT) Address offset: 0x1C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. - Page 664 Low-power timer (LPTIM) RM0430 Bit 3 TIM5_ITR1_RMP: TIMER5 input Trigger 1 remap Set and cleared by software. TIM3 output trigger Output channel of LPTIMERS Bit 2 TIM1_ITR2_RMP: TIMER1 input Trigger 2 remap Set and cleared by software. TIM3 output trigger Output channel of LPTIMERS Bits 1:0 LPT_IN1_RMP: LPTimer input Trigger 2 remap Set and cleared by software.
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Page 665: Lptim Register Map
RM0430 Low-power timer (LPTIM) 21.6.10 LPTIM register map The following table summarizes the LPTIM registers. Table 115. LPTIM register map and reset values Offset Register LPTIM_ISR 0x00 Reset value 0 0 0 0 0 0 0 LPTIM_ICR 0x04 Reset value 0 0 0 0 0 0 0 LPTIM_IER 0x08... - Page 666 Low-power timer (LPTIM) RM0430 Table 115. LPTIM register map and reset values (continued) Offset Register LPTIM_OR 0x20 Reset Value 0 0 0 Refer to Section 2.2.2 on page 56 for the register boundary addresses. 666/1284 DocID029473 Rev 3...
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Page 667: Independent Watchdog (Iwdg)
RM0430 Independent watchdog (IWDG) Independent watchdog (IWDG) 22.1 IWDG introduction The devices feature two embedded watchdog peripherals that offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value. - Page 668 Independent watchdog (IWDG) RM0430 A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. 22.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4 with FPU core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module.
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Page 669: Iwdg Registers
RM0430 Independent watchdog (IWDG) 22.4 IWDG registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 22.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res. -
Page 670: Prescaler Register (Iwdg_Pr)
Independent watchdog (IWDG) RM0430 22.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 671: Reload Register (Iwdg_Rlr)
RM0430 Independent watchdog (IWDG) 22.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value. -
Page 672: Iwdg Register Map
Independent watchdog (IWDG) RM0430 Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete) -
Page 673: Window Watchdog (Wwdg)
RM0430 Window watchdog (WWDG) Window watchdog (WWDG) 23.1 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. -
Page 674: Figure 222. Watchdog Block Diagram
Window watchdog (WWDG) RM0430 Figure 222. Watchdog block diagram The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0. -
Page 675: How To Program The Watchdog Timeout
RM0430 Window watchdog (WWDG) In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. - Page 676 Window watchdog (WWDG) RM0430 As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: ⁄ × × × t WWDG 24000 4096 21.85 ms Refer to the datasheets for the minimum and maximum values of the t WWDG.
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Page 677: Wwdg Registers
RM0430 Window watchdog (WWDG) 23.6 WWDG registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 23.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Res. -
Page 678: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0430 23.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGTB[1:0] W[6:0] Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. -
Page 679: Wwdg Register Map
RM0430 Window watchdog (WWDG) 23.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 118. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reset value WWDG_CFR W[6:0] 0x04 Reset value WWDG_SR 0x08 Reset value Refer to... -
Page 680: Advanced Encryption Standard Hardware Accelerator (Aes)
Advanced encryption standard hardware accelerator (AES) RM0430 Advanced encryption standard hardware accelerator (AES) 24.1 Introduction The AES hardware accelerator can be used to both encipher and decipher data using AES algorithm. It is a fully compliant implementation of the following standard: •... -
Page 681: Aes Functional Description
RM0430 Advanced encryption standard hardware accelerator (AES) 24.3 AES functional description Figure 224 shows the block diagram of the AES accelerator. Figure 224. AES block diagram The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length of either 256 bits or 128 bits, and an initialization vector when CBC, CTR, GCM, GMAC or CMAC chaining mode is selected. -
Page 682: Encryption And Derivation Keys
Advanced encryption standard hardware accelerator (AES) RM0430 in the AES_KEYRx registers and the AES is disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES is enabled and until the CCF flag is set to 1 by hardware. The status flag CCF in the AES_SR register is set once the computation phase is complete. -
Page 683: Aes Chaining Algorithms
RM0430 Advanced encryption standard hardware accelerator (AES) to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx registers if their content corresponds to the derivation key (previously computed by mode 2). In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the encryption key. -
Page 684: Cipher Block Chaining (Cbc)
Advanced encryption standard hardware accelerator (AES) RM0430 Figure 226. ECB decryption mode 24.5.2 Cipher block chaining (CBC) In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous cipher text block before being encrypted. To make each message unique, an initialization vector (AES_IVRx) is used during the first block processing. -
Page 685: Figure 227. Cbc Mode Encryption
RM0430 Advanced encryption standard hardware accelerator (AES) Figure 227. CBC mode encryption Figure 228. CBC mode decryption Note: When the AES is enabled, reading the AES_IVR returns the value 0x0000 0000. DocID029473 Rev 3 685/1284... - Page 686 Advanced encryption standard hardware accelerator (AES) RM0430 Suspended mode for a given message It is possible to suspend a message if another message with a higher priority needs to be processed. After sending this highest priority message, the suspended message may be resumed in both encryption or decryption mode.
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Page 687: Figure 229. Example Of Suspend Mode Management
RM0430 Advanced encryption standard hardware accelerator (AES) Figure 229. Example of suspend mode management DocID029473 Rev 3 687/1284... -
Page 688: Counter Mode (Ctr)
Advanced encryption standard hardware accelerator (AES) RM0430 24.5.3 Counter Mode (CTR) In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation with the cipher text or plain text (refer to Figure 230 Figure 231). -
Page 689: Galois Counter Mode (Gcm)
RM0430 Advanced encryption standard hardware accelerator (AES) The nonce value and 32-bit counter are accessible through the AES_IVRx register and organized like below in Figure 232: Figure 232. 32-bit counter + nonce organization In counter mode, the counter is incremented from the initialized value for each block to be processed in order to guarantee a unique sequence which is not repeated for a long time. - Page 690 Advanced encryption standard hardware accelerator (AES) RM0430 the size of the header on 64 bits and the size of the payload on 64 bits. During computation we have to distinguish between the blocks of the header and the blocks of the payload. Header •...
- Page 691 RM0430 Advanced encryption standard hardware accelerator (AES) Repeat (p), (q), (r) and (s) until ciphering or deciphering of all the payload blocks. Alternatively, DMA may be used. GCM Final Phase: • In this last step, we generate the authentication tag. Choose the combination GCMPH[1:0] = 11 in AES_CR.
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Page 692: Aes Cipher Message Authentication Code Mode (Cmac)
Advanced encryption standard hardware accelerator (AES) RM0430 Suspend mode during Payload phase: the user must respect the following steps: • Before interrupting the current message: Read 4 times the AES_DOUTR register. Make sure that busy flag is set to 0 (only in encryption mode, not necessary in decryption mode). - Page 693 RM0430 Advanced encryption standard hardware accelerator (AES) Note: In this stage, no output is provided in AES_DOUTR register. Set GCMPH=”01” in AES_CR to indicate that we are in the header phase. Enable the AES by setting EN bit in AES_CR. Insert B0 for first transfer, and then B for further transfers.
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Page 694: Data Type
Advanced encryption standard hardware accelerator (AES) RM0430 To suspend mode CMAC during header phase, the user must respect the following steps: • Before interrupting the current message: Make sure that CCF flag in AES_SR is set to 1. Clear CCF flag in AES_SR register by setting CCFC bit to 1 in AES_CR. Save AES initialization vector registers AES_IVx and AES_SUSPxR registers in the memory (AES_IVx registers are modified during header phase) Disable AES processor by setting EN in AES_CR to 0. -
Page 695: Figure 233. 128-Bit Block Construction According To The Data Type
RM0430 Advanced encryption standard hardware accelerator (AES) Figure 233. 128-bit block construction according to the data type DocID029473 Rev 3 695/1284... -
Page 696: Operating Modes
Advanced encryption standard hardware accelerator (AES) RM0430 Figure 234. 128-bit block construction according to the data type (continued) 24.9 Operating modes 24.9.1 Mode 1: encryption Disable the AES by resetting EN bit in the AES_CR register. Configure the mode 1 by programming MODE[1:0] = 00 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits. -
Page 697: Mode 2: Key Derivation
RM0430 Advanced encryption standard hardware accelerator (AES) Figure 235. Mode 1: encryption with 128-bit key length 24.9.2 Mode 2: key derivation Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 2 by programming MODE[1:0] = 01 in the AES_CR register. Note: CHMOD[2:0] bits are not significant in this case because this key derivation mode is independent from the chaining algorithm selected. -
Page 698: Mode 3: Decryption
Advanced encryption standard hardware accelerator (AES) RM0430 24.9.3 Mode 3: decryption Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 3 by programming MODE[1:0] = 10 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits. -
Page 699: Aes Dma Interface
RM0430 Advanced encryption standard hardware accelerator (AES) forced to CTR decryption mode if the software writes MODE[1:0] = 11 and CHMOD[2:0] = 010. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if the CBC mode is selected. -
Page 700: Error Flags
Advanced encryption standard hardware accelerator (AES) RM0430 Note: For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN bit and DMAOUTEN bits in the AES_CR register have no effect during this mode. The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in this case. -
Page 701: Processing Time
RM0430 Advanced encryption standard hardware accelerator (AES) 24.12 Processing time The following tables summarize the time required to process a 128-bit block for each mode of operation. Table 119. Processing time (in clock cycle) Computation Output Mode of operation Input phase Total phase phase... -
Page 702: Aes Interrupts
Advanced encryption standard hardware accelerator (AES) RM0430 24.13 AES interrupts Table 122. AES interrupt requests Enable Exit from Interrupt event Event flag control bit Wait AES computation completed flag CCFIE AES read error flag RDERR ERRIE AES write error flag WRERR ERRIE 702/1284... -
Page 703: Aes Registers
RM0430 Advanced encryption standard hardware accelerator (AES) 24.14 AES registers 24.14.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SIZE Res. GCMPH[1:0] ERRIE CCFIE ERRC CCFC... - Page 704 Advanced encryption standard hardware accelerator (AES) RM0430 Bit 9 CCFIE: CCF flag interrupt enable An interrupt is generated if the CCF flag is set. 0: CCF interrupt disabled 1: CCF interrupt enabled Bit 8 ERRC: Error clear Writing 1 to this bit clears the RDERR and WRERR flags. This bit is always read low.
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Page 705: Aes Status Register (Aes_Sr)
RM0430 Advanced encryption standard hardware accelerator (AES) 24.14.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. - Page 706 Advanced encryption standard hardware accelerator (AES) RM0430 Bit 2 WRERR: Write error flag This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register.
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Page 707: Aes Data Input Register (Aes_Dinr)
RM0430 Advanced encryption standard hardware accelerator (AES) 24.14.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 DINR[31:16] DINR[15:0] Bits 31:0 DINR[31:0]: Data input register This register must be written 4 times during the input phase: – In mode 1 (encryption), 4 words must be written which represent the plain text from MSB to LSB. –... -
Page 708: Aes Key Register 0 (Aes_Keyr0) (Lsb: Key [31:0])
Advanced encryption standard hardware accelerator (AES) RM0430 24.14.5 AES key register 0 (AES_KEYR0) (LSB: key [31:0]) Address offset: 0x10 Reset value: 0x0000 0000 KEYR0[31:16] KEYR0[15:0] Bits 31:0 KEYR0[31:0]: Data output register (LSB key [31:0]) This register must be written before the EN bit in the AES_CR register is set: In mode 1 (encryption), mode 2 (key derivation) and mode 4 (key derivation + decryption), the value to be written represents the encryption key from LSB, meaning key [31:0]. -
Page 709: Aes Key Register 2 (Aes_Keyr2) (Key [95:64])
RM0430 Advanced encryption standard hardware accelerator (AES) 24.14.7 AES key register 2 (AES_KEYR2) (key [95:64]) Address offset: 0x18 Reset value: 0x0000 0000 KEYR2[31:16] KEYR2[15:0] Bits 31:0 KEYR2[31:0]: Data output register (key [95:64]) Refer to the description of AES_KEYR0. 24.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) Address offset: 0x1C Reset value: 0x0000 0000 KEYR3[31:16]... -
Page 710: Aes Initialization Vector Register 1 (Aes_Ivr1) (Ivr[63:32])
Advanced encryption standard hardware accelerator (AES) RM0430 Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR[31:0]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. –... -
Page 711: Aes Initialization Vector Register 2 (Aes_Ivr2) (Ivr[95:64])
RM0430 Advanced encryption standard hardware accelerator (AES) 24.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) Address offset: 0x28 Reset value: 0x0000 0000 IVR2[31:16] IVR2[15:0] Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: –... -
Page 712: Aes Key Register 5 (Aes_Keyr5) (Key[191:160])
Advanced encryption standard hardware accelerator (AES) RM0430 KEYR431:16] KEYR4[15:0] Bits 31:0 KEYR4[31:0]: Data output register (key [159:128]) Same description as AES_KEYR0 for the key[159:128]. 24.14.14 AES key register 5 (AES_KEYR5) (key[191:160]) Address offset: 0x34 Reset value: 0x0000 0000 KEYR5[31:16] KEYR5[15:0] Bits 31:0 KEYR5[31:0]: Data output register (key [191:160]) Same description as AES_KEYR0 for the key[191:160]. - Page 713 RM0430 Advanced encryption standard hardware accelerator (AES) KEYR731:16] KEYR7[15:0] Bits 31:0 KEYR7[31:0]: Data output register (MSB key [255:224]) Same description as AES_KEYR0 for the key[255:224]. Note: The key registers from 4 to 7 are used only when 256-bit key length is selected. These registers have no effect when 128-bit key length is selected (only key registers from 0 to 3 are used).
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Page 714: Aes Register Map
Advanced encryption standard hardware accelerator (AES) RM0430 24.14.17 AES registers (AES_SUSPxR) (x = 0..7) Suspend Address offset: 0x040 (AES_SUSP0R) to 0x05C (AES_SUSP7R) Reset value: 0x0000 0000 These registers contain the complete internal register states of the AES processor when the GCM/GMAC is selected, and are useful when a suspend has to be done because a high- priority task has to use the AES processor while it is already in use by another task. - Page 715 RM0430 Advanced encryption standard hardware accelerator (AES) Table 123. AES register map (continued) Offset Register AES_KEYR3 AES_KEYR3[31:0] 0x001C Reset value AES_IVR0 AES_IVR0[31:0] 0x0020 Reset value AES_IVR1 AES_IVR1[31:0] 0x0024 Reset value AES_IVR2 AES_IVR2[31:0] 0x0028 Reset value AES_IVR3 AES_IVR3[31:0] 0x002C Reset value AES_KEYR4 AES_KEYR4[31:0] 0x0030...
- Page 716 Real-time clock (RTC) RM0430 Real-time clock (RTC) 25.1 Introduction The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC also includes an automatic wakeup unit to manage low power modes.
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Page 717: Rtc Functional Description
RM0430 Real-time clock (RTC) – 0.95 ppm accuracy, obtained in a calibration window of several seconds • Timestamp function for event saving (1 event) • Tamper detection: – 2 tamper events with configurable filter and internal pull-up. • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs. -
Page 718: Real-Time Clock And Calendar
Real-time clock (RTC) RM0430 is given by the following formula: ck_apre RTCCLK -------------------------------------- - CK_APRE PREDIV_A The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. is given by the following formula: ck_spre RTCCLK... -
Page 719: Periodic Auto-Wakeup
RM0430 Real-time clock (RTC) RTC_ALRMASSR and RTC_ALRMBSSR registers. The alarm interrupts are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register. Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output. - Page 720 Real-time clock (RTC) RM0430 RTC register write protection After system reset, the RTC registers are protected against parasitic write access with the DBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable RTC registers write access. After backup domain reset, all the RTC registers are write-protected.
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Page 721: Reading The Calendar
RM0430 Real-time clock (RTC) Programming the alarm A similar procedure must be followed to program or update the programmable alarm (Alarm A or Alarm B): Clear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B. Poll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm registers is allowed. -
Page 722: Resetting The Rtc
Real-time clock (RTC) RM0430 After waking up from low power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers. The RSF bit must be cleared after wakeup and not before entering low power mode. Note: After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. -
Page 723: Rtc Reference Clock Detection
RM0430 Real-time clock (RTC) RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR. RTC_SSR contains the value of the synchronous prescaler’s counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. -
Page 724: Rtc Coarse Digital Calibration
Real-time clock (RTC) RM0430 If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge. -
Page 725: Rtc Smooth Digital Calibration
RM0430 Real-time clock (RTC) The ck_spre clock frequency is only modified during the first 2xDC minutes of the 64-minute cycle. For example, when DC equals 1, only the first 2 minutes are modified. This means that the first 2xDC minutes of each 64-minute cycle have, once per minute, one second either shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre cycle represents 128 RTCCLK cycles (with PREDIV_A+1=128). - Page 726 Real-time clock (RTC) RM0430 Calibration when PREDIV_A<3 The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0.
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Page 727: Timestamp Function
RM0430 Real-time clock (RTC) Re-calibration on-the-fly The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process: Poll the RTC_ISR/RECALPF (re-calibration pending flag). If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1 Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect. - Page 728 Real-time clock (RTC) RM0430 when the V power is switched off. They are not reset by system reset or when the device wakes up from Standby mode. They are reset by a backup domain reset The backup registers are reset when a tamper detection event occurs (see Section 25.6.20: RTC backup registers (RTC_BKPxR) Tamper detection initialization on page...
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Page 729: Calibration Clock Output
RM0430 Real-time clock (RTC) samples are observed at the level designated by the TAMPxTRG bits (TAMP1TRG/TAMP2TRG). The TAMPER inputs are pre-charged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper inputs. -
Page 730: Rtc And Low Power Modes
Real-time clock (RTC) RM0430 Note: Once RTC_ALARM is enabled, it has priority over RTC_CALIB (COE bit is don't care on RTC_AF1). When RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in output alternate function. 25.4 RTC and low power modes Table 124. -
Page 731: Table 125. Interrupt Control Bits
RM0430 Real-time clock (RTC) Table 125. Interrupt control bits Enable Exit the Exit the Exit the Interrupt event Event flag control Sleep Stop Standby mode mode mode Alarm A ALRAF ALRAIE Alarm B ALRBF ALRBIE Wakeup WUTF WUTIE TimeStamp TSIE Tamper1 detection TAMP1F TAMPIE... -
Page 732: Rtc Registers
Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register is write protected. -
Page 733: Rtc Date Register (Rtc_Dr)
RM0430 Real-time clock (RTC) 25.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration Reading the calendar. Address offset: 0x04 Backup domain reset value: 0x0000_2101 System reset: 0x0000 2101 when BYPSHAD = 0. -
Page 734: Rtc Control Register (Rtc_Cr)
Real-time clock (RTC) RM0430 25.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL BKP SUB1H ADD1H TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE DCE FMT BYPSHAD REFCKON TSEDGE WUCKSEL[2:0] Bits 31:24 Reserved, must be kept at reset value. - Page 735 RM0430 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Timestamp interrupt enable 0: Timestamp Interrupt disable 1: Timestamp Interrupt enable...
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Page 736: Rtc Initialization And Status Register (Rtc_Isr)
Real-time clock (RTC) RM0430 Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz) 0: Reference clock detection disabled 1: Reference clock detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Timestamp event active edge 0: TIMESTAMP rising edge generates a timestamp event 1: TIMESTAMP falling edge generates a timestamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection... - Page 737 RM0430 Real-time clock (RTC) Bit 11 TSF: Timestamp flag This flag is set by hardware when a timestamp event occurs. This flag is cleared by software by writing 0. Bit 10 WUTF: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0.
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Page 738: Rtc Prescaler Register (Rtc_Prer)
Real-time clock (RTC) RM0430 Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR. It is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set. -
Page 739: Rtc Wakeup Timer Register (Rtc_Wutr)
RM0430 Real-time clock (RTC) Note: This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 720 This register is write protected. The write access procedure is described in RTC register write protection on page 720. - Page 740 Real-time clock (RTC) RM0430 Bits 31:8 Reserved, must be kept at reset value Bit 7 DCS: Digital calibration sign 0: Positive calibration: calendar update frequency is increased 1: Negative calibration: calendar update frequency is decreased Bits 6:5 Reserved, must be kept at reset value. Bits 4:0 DC[4:0]: Digital calibration DCS = 0 (positive calibration) 00000: +0 ppm...
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Page 741: Rtc Alarm A Register (Rtc_Alrmar)
Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode. -
Page 742: Rtc Alarm B Register (Rtc_Alrmbr)
Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode. -
Page 743: Rtc Write Protection Register (Rtc_Wpr)
RM0430 Real-time clock (RTC) 25.6.10 RTC write protection register (RTC_WPR) Address offset: 0x24 Backup domain reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 744: Rtc Shift Control Register (Rtc_Shiftr)
Real-time clock (RTC) RM0430 25.6.12 RTC shift control register (RTC_SHIFTR) Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SUBFS[14:0] Bit 31 ADD1S: Add one second 0: No effect... -
Page 745: Rtc Time Stamp Time Register (Rtc_Tstr)
Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. -
Page 746: Rtc Timestamp Sub Second Register (Rtc_Tsssr)
Real-time clock (RTC) RM0430 Bits 31:16 Reserved, must be kept at reset value. Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format Note:... - Page 747 RM0430 Real-time clock (RTC) Bits 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 2 pulses (frequency increased by 488.5 ppm).
- Page 748 Real-time clock (RTC) RM0430 Bit 16 TAMP1INSEL: TAMPER1 mapping 0: RTC_AF1 used as TAMPER1 Note: TAMP1E must be reset when TAMP1INSEL is changed to avoid unwanted setting of TAMP1F. Bit 15 TAMPPUDIS: TAMPER pull-up disable This bit determines if each of the tamper pins are pre-charged before each sample. 0: Precharge tamper pins before sampling (enable internal pull-up) 1: Disable precharge of tamper pins Note:...
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Page 749: Rtc Alarm A Sub Second Register (Rtc_Alrmassr)
RM0430 Real-time clock (RTC) Bit 1 TAMP1TRG: Active level for tamper 1 if TAMPFLT != 00: 0: TAMPER1 staying low triggers a tamper detection event. 1: TAMPER1 staying high triggers a tamper detection event. if TAMPFLT = 00: 0: TAMPER1 rising edge triggers a tamper detection event. 1: TAMPER1 falling edge triggers a tamper detection event. -
Page 750: Rtc Alarm B Sub Second Register (Rtc_Alrmbssr)
Real-time clock (RTC) RM0430 Note: This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 720 25.6.19 RTC alarm B sub second register (RTC_ALRMBSSR) Address offset: 0x48... -
Page 751: Rtc Register Map
This register is reset on a tamper detection event, as long as TAMPxF=1. 25.6.21 RTC register map Table 126. RTC register map and reset values Offset Register RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] [1:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0]... - Page 752 Table 126. RTC register map and reset values (continued) Offset Register RTC_SSR SS[15:0] 0x28 Reset value RTC_SHIFTR SUBFS[14:0] 0x2C Reset value RTC_TSTR HU[3:0] MNU[3:0] ST[2:0] SU[3:0] 0x30 Reset value RTC_TSSSR SS[15:0] 0x38 Reset value RTC_ CALR CALM[8:0] 0x3C Reset value RTC_ MASKSS[3:0]...
- Page 753 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.1 Introduction The I C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I bus-specific sequencing, protocol, arbitration and timing.
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Page 754: Fmpi2C Implementation
Independent clock: a choice of independent clock sources allowing the FMPI2C communication speed to be independent from the PCLK reprogramming 26.3 FMPI2C implementation This manual describes the full set of features implemented in FMPI2C1. Table 127. STM32F413/423 FMPI2C implementation I2C features I2CFMP1 Independent clock SMBus Wakeup from Stop mode 1. -
Page 755: Fmpi2C Block Diagram
This independent clock source can be selected for either of the following clock sources: • PCLK1: APB1 clock (default value) • HSI: high speed internal oscillator • SYSCLK: system clock Refer to Section 6: Reset and clock control (RCC) for STM32F413/423 for more details. DocID029473 Rev 3 755/1284... -
Page 756: Fmpi2C Clock Requirements
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.2 FMPI2C clock requirements The FMPI2C kernel is clocked by FMPI2CCLK. The FMPI2CCLK period t must respect the following conditions: I2CCLK I2CCLK < (tLOW - tfilters ) / 4 and I2CCLK < tHIGH with: LOW: SCL low time and tHIGH : SCL high time when enabled, sum of the delays brought by the analog filter and by the digital filter. - Page 757 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 243. I C bus protocol Acknowledge can be enabled or disabled by software. The FMPI2C interface addresses can be selected by software. DocID029473 Rev 3 757/1284...
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Page 758: Fmpi2C Initialization
The FMPI2C peripheral clock must be configured and enabled in the clock controller (refer Section 6: Reset and clock control (RCC) for STM32F413/423). Then the FMPI2C can be enabled by setting the PE bit in the FMPI2C_CR1 register. When the FMPI2C is disabled (PE=0), the I C performs a software reset. -
Page 759: Figure 244. Setup And Hold Timings
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface FMPI2C timings The timings must be configured in order to guarantee a correct data hold and setup time, used in master and slave modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window Figure 244. - Page 760 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 • When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is where = SDADEL x t = (PRESC+1) SDADEL PRESC I2CCLK PRESC I2CCLK impacts the hold time SDADEL HD;DAT.
- Page 761 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface The SDA and SCL transition time values to be used are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application. Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t...
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Page 762: Software Reset
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 245. FMPI2C initialization flowchart 26.4.5 Software reset A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and communication control bits, as well as status bits come back to their reset value. -
Page 763: Data Transfer
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.4.6 Data transfer The data transfer is managed through transmit and receive data registers and a shift register. Reception The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0). -
Page 764: Figure 247. Data Transmission
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Transmission If the FMPI2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the 9th SCL pulse (the Acknowledge pulse). Then the shift register content is shifted out on SDA line. If TXE=1, meaning that no data is written yet in FMPI2C_TXDR, SCL line is stretched low until FMPI2C_TXDR is written. -
Page 765: Fmpi2C Slave Mode
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface When RELOAD=0 in master mode, the counter can be used in 2 modes: • Automatic end mode (AUTOEND = ‘1’ in the FMPI2C_CR2 register). In this mode, the master automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bit field has been transferred. - Page 766 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 By default, the slave uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the master does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in the FMPI2C_CR1 register.
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Page 767: Figure 248. Slave Initialization Flowchart
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Slave Byte Control mode In order to allow byte ACK control in slave reception mode, Slave Byte Control mode must be enabled by setting the SBC bit in the FMPI2C_CR1 register. This is required to be compliant with SMBus standards. - Page 768 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Slave transmitter A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register. The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte to be transmitted.
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Page 769: Figure 249. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=0
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 249. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=0 DocID029473 Rev 3 769/1284... -
Page 770: Figure 250. Transfer Sequence Flowchart For Fmpi2C Slave Transmitter, Nostretch=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 250. Transfer sequence flowchart for FMPI2C slave transmitter, NOSTRETCH=1 770/1284 DocID029473 Rev 3... -
Page 771: Figure 251. Transfer Bus Diagrams For Fmpi2C Slave Transmitter
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 251. Transfer bus diagrams for FMPI2C slave transmitter DocID029473 Rev 3 771/1284... -
Page 772: Figure 252. Transfer Sequence Flowchart For Slave Receiver With Nostretch=0
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Slave receiver RXNE is set in FMPI2C_ISR when the FMPI2C_RXDR is full, and generates an interrupt if RXIE is set in FMPI2C_CR1. RXNE is cleared when FMPI2C_RXDR is read. When a STOP is received and STOPIE is set in FMPI2C_CR1, STOPF is set in FMPI2C_ISR and an interrupt is generated. -
Page 773: Figure 253. Transfer Sequence Flowchart For Slave Receiver With Nostretch=1
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 253. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 Figure 254. Transfer bus diagrams for FMPI2C slave receiver DocID029473 Rev 3 773/1284... -
Page 774: Fmpi2C Master Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.8 FMPI2C master mode FMPI2C master initialization Before enabling the peripheral, the FMPI2C master clock must be configured by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window. -
Page 775: Figure 255. Master Clock Generation
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 255. Master clock generation Caution: In order to be I C or SMBus compliant, the master clock must respect the timings given below: DocID029473 Rev 3 775/1284... - Page 776 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Table 130. I C-SMBUS specification clock timings Standard- Fast-mode Fast-mode SMBUS mode (Sm) (Fm) Plus (Fm+) Symbol Parameter Unit SCL clock frequency 1000 Hold time (repeated) START 0.26 µs HD:STA condition Set-up time for a repeated 0.26 µs SU:STA...
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Page 777: Figure 256. Master Initialization Flowchart
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Note: The START bit is reset by hardware when the slave address has been sent on the bus, whatever the received acknowledge value. The START bit is also reset by hardware if an arbitration loss occurs. -
Page 778: Figure 258. 10-Bit Address Read Access With Head10R=1
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 • If the master addresses a 10-bit address slave, transmits data to this slave and then reads data from the same slave, a master transmission flow must be done first. Then a repeated start is set with the 10 bit slave address configured with HEAD10R=1. In this case the master sends this sequence: ReStart + Slave address 10-bit header Read. -
Page 779: Figure 259. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N≤255 Bytes
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 259. Transfer sequence flowchart for FMPI2C master transmitter for N≤255 bytes DocID029473 Rev 3 779/1284... -
Page 780: Figure 260. Transfer Sequence Flowchart For Fmpi2C Master Transmitter For N>255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 260. Transfer sequence flowchart for FMPI2C master transmitter for N>255 bytes 780/1284 DocID029473 Rev 3... -
Page 781: Figure 261. Transfer Bus Diagrams For Fmpi2C Master Transmitter
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 261. Transfer bus diagrams for FMPI2C master transmitter DocID029473 Rev 3 781/1284... - Page 782 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Master receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1 register.
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Page 783: Figure 262. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N≤255 Bytes
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 262. Transfer sequence flowchart for FMPI2C master receiver for N≤255 bytes DocID029473 Rev 3 783/1284... -
Page 784: Figure 263. Transfer Sequence Flowchart For Fmpi2C Master Receiver For N >255 Bytes
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 263. Transfer sequence flowchart for FMPI2C master receiver for N >255 bytes 784/1284 DocID029473 Rev 3... -
Page 785: Figure 264. Transfer Bus Diagrams For Fmpi2C Master Receiver
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 264. Transfer bus diagrams for FMPI2C master receiver DocID029473 Rev 3 785/1284... -
Page 786: Fmpi2C_Timingr Register Configuration Examples
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.9 FMPI2C_TIMINGR register configuration examples The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain timings compliant with the I C specification. In order to get more accurate configuration values, please refer to the application note: I C timing configuration tool (AN4235) and the associated software STSW-STM32126. - Page 787 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface For more details of the SMBus Address Resolution Protocol, refer to SMBus specification version 2.0 (http://smbus.org). Received Command and Data acknowledge control A SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting SBC bit in FMPI2C_CR1 register.
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Page 788: Table 131. Smbus Timeout Specifications
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Timeouts This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined in SMBus specification version 2.0. Table 131. SMBus timeout specifications Limits Symbol Parameter Unit Detect clock low timeout TIMEOUT Cumulative clock low extend time (slave device) LOW:SEXT... - Page 789 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bus idle detection A master can assume that the bus is free if it detects that the clock and data signals have been high for t greater than t . (refer to Table 130: I2C-SMBUS specification clock IDLE HIGH timings)
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Page 790: Table 132. Smbus With Pec Configuration
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Table 132. SMBUS with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Master Tx/Rx NBYTES + PEC+ STOP Master Tx/Rx NBYTES + PEC + ReSTART Slave Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the FMPI2C_TIMEOUTR register. -
Page 791: Table 134. Examples Of Timeoutb Settings For Various Fmpi2Cclk Frequencies
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Refer to Table 135: Examples of TIMEOUTA settings for various FMPI2CCLK frequencies (max tIDLE = 50 µs) Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is set. SMBus: 26.4.12 FMPI2C_TIMEOUTR register configuration examples This section is relevant only when SMBus feature is supported. -
Page 792: Smbus Slave Mode
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.4.13 SMBus slave mode This section is relevant only when SMBus feature is supported. Please refer to Section 26.3: FMPI2C implementation. In addition to FMPI2C slave transfer management (refer to Section 26.4.7: FMPI2C slave mode) some additional software flowcharts are provided to support SMBus. -
Page 793: Figure 267. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 267. Transfer bus diagrams for SMBus slave transmitter (SBC=1) SMBus Slave receiver When the FMPI2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1). -
Page 794: Figure 268. Transfer Sequence Flowchart For Smbus Slave Receiver N Bytes + Pec
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 268. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC 794/1284 DocID029473 Rev 3... -
Page 795: Figure 269. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 269. Bus transfer diagrams for SMBus slave receiver (SBC=1) This section is relevant only when SMBus feature is supported. Please refer to Section 26.3: FMPI2C implementation. In addition to FMPI2C master transfer management (refer to Section 26.4.8: FMPI2C master mode) some additional software flowcharts are provided to support SMBus. -
Page 796: Figure 270. Bus Transfer Diagrams For Smbus Master Transmitter
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 When the SMBus master wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYTES-1 have been transmitted, the FMPI2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low. - Page 797 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface SMBus Master receiver When the SMBus master wants to receive the PEC followed by a STOP at the end of the transfer, automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the slave address must be programmed, before setting the START bit.
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Page 798: Error Conditions
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Figure 271. Bus transfer diagrams for SMBus master receiver 26.4.14 Error conditions The following are the error conditions which may cause communication to fail. Bus error (BERR) A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of 9 SCL clock pulses. - Page 799 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters address recognition state like for a correct START condition. When a bus error is detected, the BERR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the FMPI2C_CR1 register.
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Page 800: Dma Requests
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Timeout Error (TIMEOUT) This section is relevant only when the SMBus feature is supported. Please refer to Section 26.3: FMPI2C implementation. A timeout error occurs for any of these conditions: • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout. - Page 801 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface NBYTES counter. Refer to Master transmitter on page 778. • In slave mode: – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
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Page 802: Fmpi2C Interrupts
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.6 FMPI2C interrupts The table below gives the list of FMPI2C interrupt requests. Table 137. FMPI2C Interrupt requests Event flag/Interrupt Interrupt enable Interrupt event Event flag clearing method control bit Read FMPI2C_RXDR Receive buffer not empty RXNE RXIE register... -
Page 803: Fmpi2C Registers
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Figure 272. FMPI2C interrupt mapping diagram 26.7 FMPI2C registers Refer to Section 1.1 on page 51 for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit). 26.7.1 Control register 1 (FMPI2C_CR1) Address offset: 0x00... - Page 804 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 23 PECEN: PEC enable 0: PEC calculation disabled 1: PEC calculation enabled Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Please refer to Section 26.3: FMPI2C implementation.
- Page 805 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 13 Reserved, must be kept at reset value. Bit 12 ANFOFF: Analog noise filter OFF 0: Analog noise filter enabled 1: Analog noise filter disabled Note: This bit can only be programmed when the FMPI2C is disabled (PE = 0). Bits 11:8 DNF[3:0]: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input.
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Page 806: Control Register 2 (Fmpi2C_Cr2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: When PE=0, the FMPI2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles. - Page 807 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bits 23:16 NBYTES[7:0]: Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don’t care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed. Bit 15 NACK: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0.
- Page 808 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 10 RD_WRN: Transfer direction (master mode) 0: Master requests a write transfer. 1: Master requests a read transfer. Note: Changing this bit when the START bit is set is not allowed. Bits 9:8 SADD[9:8]: Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are don’t care In 10-bit addressing mode (ADD10 = 1):...
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Page 809: Own Address 1 Register (Fmpi2C_Oar1)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.3 Own address 1 register (FMPI2C_OAR1) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. -
Page 810: Own Address 2 Register (Fmpi2C_Oar2)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.4 Own address 2 register (FMPI2C_OAR2) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. -
Page 811: Timing Register (Fmpi2C_Timingr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.5 Timing register (FMPI2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: No wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale FMPI2CCLK in order to generate the clock period t used for PRESC data setup and hold counters (refer to... -
Page 812: Timeout Register (Fmpi2C_Timeoutr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.6 Timeout register (FMPI2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. -
Page 813: Interrupt And Status Register (Fmpi2C_Isr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.7 Interrupt and status register (FMPI2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIME BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value. - Page 814 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 11 PECERR: PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.
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Page 815: Interrupt Clear Register (Fmpi2C_Icr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Bit 2 RXNE: Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read. Note: This bit is cleared by hardware when PE=0. -
Page 816: Pec Register (Fmpi2C_Pecr)
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 Bit 10 OVRCF: Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register. Bit 9 ARLOCF: Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register. Bit 8 BERRCF: Bus error flag clear Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register. -
Page 817: Receive Data Register (Fmpi2C_Rxdr)
RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface 26.7.10 Receive data register (FMPI2C_RXDR) Address offset: 0x24 Reset value: 0x0000 0000 Access: No wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 818: Fmpi2C Register Map
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0430 26.7.12 FMPI2C register map The table below provides the FMPI2C register map and reset values. Table 138. FMPI2C register map and reset values Offset Register FMPI2C_CR1 DNF[3:0] Reset value FMPI2C_CR2 NBYTES[7:0] SADD[9:0] Reset value FMPI2C_OAR1 OA1[9:0] Reset value... - Page 819 RM0430 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface Table 138. FMPI2C register map and reset values (continued) Offset Register FMPI2C_TXDR TXDATA[7:0] 0x28 Reset value Refer to Section 2.2.2 on page 56 for the register boundary addresses. DocID029473 Rev 3 819/1284...
- Page 820 Inter-integrated circuit (I C) interface RM0430 Inter-integrated circuit (I C) interface 27.1 C introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.
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Page 821: Inter-Integrated Circuit (I 2 C) Interface
RM0430 Inter-integrated circuit (I C) interface 27.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –... -
Page 822: Mode Selection
Inter-integrated circuit (I C) interface RM0430 Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I C interface implementation. 27.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel... - Page 823 RM0430 Inter-integrated circuit (I C) interface The block diagram of the I C interface is shown in Figure 274. Figure 274. I C block diagram 1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 27.3.2 C slave mode By default the I...
- Page 824 Inter-integrated circuit (I C) interface RM0430 Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0), where xx denotes the two most significant bits of the address. Header or address not matched: the interface ignores it and waits for another Start condition.
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Page 825: Figure 275. Transfer Sequence Diagram For Slave Transmitter
RM0430 Inter-integrated circuit (I C) interface Figure 275. Transfer sequence diagram for slave transmitter 1. The EV1 and EV3_1 events stretch SCL low until the end of the corresponding software sequence. 2. The EV3 event stretches SCL low if the software sequence is not completed before the end of the next byte transmission Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the... -
Page 826: Figure 276. Transfer Sequence Diagram For Slave Receiver
Inter-integrated circuit (I C) interface RM0430 Figure 276. Transfer sequence diagram for slave receiver 1. The EV1 event stretches SCL low until the end of the corresponding software sequence. 2. The EV2 event stretches SCL low if the software sequence is not completed before the end of the next byte reception. - Page 827 RM0430 Inter-integrated circuit (I C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
- Page 828 Inter-integrated circuit (I C) interface RM0430 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
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Page 829: Figure 277. Transfer Sequence Diagram For Master Transmitter
RM0430 Inter-integrated circuit (I C) interface Figure 277. Transfer sequence diagram for master transmitter 1. The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence. 2. The EV8 event stretches SCL low if the software sequence is not complete before the end of the next byte transmission. DocID029473 Rev 3 829/1284... - Page 830 Inter-integrated circuit (I C) interface RM0430 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
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Page 831: Figure 278. Transfer Sequence Diagram For Master Receiver
RM0430 Inter-integrated circuit (I C) interface Figure 278. Transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3. - Page 832 Inter-integrated circuit (I C) interface RM0430 For N >2 -byte reception, from N-2 data reception • Wait until BTF = 1 (data N-2 in DR, data N-1 in shift register, SCL stretched low until data N-2 is read) • Set ACK low •...
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Page 833: Programmable Noise Filter
RM0430 Inter-integrated circuit (I C) interface Overrun/underrun error (OVR) An overrun error can occur in slave mode when clock stretching is disabled and the I interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR has not been read, before the next byte is received by the interface. -
Page 834: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0430 Note: For each frequency range, the constraint is given based on the worst case which is the minimum frequency of the range. Greater DNF values can be used if the system can support maximum hold time violation. 27.3.6 SDA/SCL line control •... - Page 835 RM0430 Inter-integrated circuit (I C) interface Table 140. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed Logic levels are V dependent Different address types (reserved, dynamic etc.)
- Page 836 Inter-integrated circuit (I C) interface RM0430 SMBus alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin. SMBA is a wired-AND signal just as the SCL and SDA signals are. SMBA is used in conjunction with the SMBus General Call Address.
- Page 837 RM0430 Inter-integrated circuit (I C) interface 27.3.8 DMA requests DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. The DMA must be initialized and enabled before the I2C data transfer. The DMAEN bit must be set in the I2C_CR2 register before the ADDR event.
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Page 838: Packet Error Checking
Inter-integrated circuit (I C) interface RM0430 Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received. - Page 839 RM0430 Inter-integrated circuit (I C) interface be set before the ACK of the CRC reception in slave mode. It must be set when the ACK is set low in master mode. • A PECERR error flag/interrupt is also available in the I2C_SR1 register. •...
- Page 840 Inter-integrated circuit (I C) interface RM0430 Figure 279. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBALERT 840/1284 DocID029473 Rev 3...
- Page 841 RM0430 Inter-integrated circuit (I C) interface 27.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M4 with FPU core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to .
- Page 842 Inter-integrated circuit (I C) interface RM0430 Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
- Page 843 RM0430 Inter-integrated circuit (I C) interface Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the end of the current communication, when back to IDLE state.
- Page 844 Inter-integrated circuit (I C) interface RM0430 ITERREN: Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 –...
- Page 845 RM0430 Inter-integrated circuit (I C) interface 27.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. ADD[9:8] ADD[7:1] ADD0 MODE Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
- Page 846 Inter-integrated circuit (I C) interface RM0430 27.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. DR[7:0] Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus.
- Page 847 RM0430 Inter-integrated circuit (I C) interface Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
- Page 848 Inter-integrated circuit (I C) interface RM0430 Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
- Page 849 RM0430 Inter-integrated circuit (I C) interface Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
- Page 850 Inter-integrated circuit (I C) interface RM0430 27.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
- Page 851 RM0430 Inter-integrated circuit (I C) interface Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
- Page 852 Inter-integrated circuit (I C) interface RM0430 Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
- Page 853 RM0430 Inter-integrated circuit (I C) interface 27.6.10 C FLTR register (I2C_FLTR) Address offset: 0x24 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ANOFF DNF[3:0] Bits 15:5 Reserved, must be kept at reset value Bit 4 ANOFF: Analog noise filter OFF 0: Analog noise filter enable 1: Analog noise filter disable Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
- Page 854 Inter-integrated circuit (I C) interface RM0430 27.6.11 C register map The table below provides the I C register map and reset values. Table 142. I C register map and reset values Offset Register I2C_CR1 0x00 Reset value I2C_CR2 FREQ[5:0] 0x04 Reset value ADD[ I2C_OAR1...
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Page 855: Usart Introduction
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) 28.1 USART introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator. -
Page 856: Usart Main Features
Universal synchronous asynchronous receiver transmitter (USART) RM0430 28.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Configurable oversampling method by 16 or by 8 to give flexibility between speed and clock tolerance • Fractional baud rate generator systems –... -
Page 857: Usart Implementation
RM0430 Universal synchronous asynchronous receiver transmitter (USART) – Receive data register full – Idle line received – Overrun error – Framing error – Noise error – Parity error • Multiprocessor communication - enter into mute mode if address match does not occur •... - Page 858 Universal synchronous asynchronous receiver transmitter (USART) RM0430 RX: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. TX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration.
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Page 859: Figure 280. Usart Block Diagram
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Figure 280. USART block diagram PWDATA PRDATA Write Read (Data register) DR (CPU or DMA) (CPU or DMA) Receive data register (RDR) Transmit data register (TDR) IrDA SW_RX Receive Shift Register Transmit Shift Register ENDEC block IRDA_OUT... -
Page 860: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0430 28.4.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 281). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”... -
Page 861: Transmitter
RM0430 Universal synchronous asynchronous receiver transmitter (USART) 28.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin. -
Page 862: Figure 282. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Figure 282. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next data frame parity Data frame Next Start start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible... -
Page 863: Figure 283. Tc/Txe Behavior When Transmitting
RM0430 Universal synchronous asynchronous receiver transmitter (USART) When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. -
Page 864: Receiver
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Idle characters Setting the TE bit drives the USART to send an idle frame before the first data frame. 28.4.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. - Page 865 RM0430 Universal synchronous asynchronous receiver transmitter (USART) Character reception During an USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register.
- Page 866 Universal synchronous asynchronous receiver transmitter (USART) RM0430 The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
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Page 867: Table 144. Noise Detection From Sampled Data
RM0430 Universal synchronous asynchronous receiver transmitter (USART) receiver tolerance to clock deviation). In this case the NF bit will never be set. When noise is detected in a frame: • The NF bit is set at the rising edge of the RXNE bit. •... - Page 868 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Table 144. Noise detection from sampled data (continued) Sampled value NE status Received bit value Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise.
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Page 869: Fractional Baud Rate Generation
RM0430 Universal synchronous asynchronous receiver transmitter (USART) be set. The second stop bit is not checked for framing error. The RXNE flag will be set at the end of the first stop bit. 28.4.4 Fractional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the Mantissa and Fraction values of USARTDIV. - Page 870 Universal synchronous asynchronous receiver transmitter (USART) RM0430 This leads to: DIV_Fraction = 16*0d0.99 = 0d15.84 The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be added up to the mantissa DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000 How to derive USARTDIV from USART_BRR register values when OVER8=1 Example 1:...
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Page 871: Oversampling By 16
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Table 145. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate7 = 8 MHz = 12 MHz PCLK PCLK Value... - Page 872 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Table 146. Error calculation for programmed baud rates at f = 8 MHz or f = 12 MHz, PCLK PCLK oversampling by 8 (continued) Oversampling by 8 (OVER8 = 1) Baud rate = 8 MHz = 12 MHz PCLK PCLK...
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Page 873: Oversampling By 8
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Table 148. Error calculation for programmed baud rates at f = 16 MHz or f = 24 MHz, PCLK PCLK oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate = 16 MHz = 24 MHz PCLK PCLK Value... - Page 874 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Table 149. Error calculation for programmed baud rates at f = 8 MHz or f = 16 MHz, PCLK PCLK oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 8 MHz = 16 MHz PCLK PCLK...
- Page 875 RM0430 Universal synchronous asynchronous receiver transmitter (USART) Table 151. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1)(2) oversampling by 16 Oversampling by 16 (OVER8=0) Baud rate = 30 MHz = 60 MHz PCLK PCLK...
- Page 876 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Table 152. Error calculation for programmed baud rates at f = 30 MHz or f = 60 MHz, PCLK PCLK (1) (2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 30 MHz =60 MHz PCLK PCLK...
- Page 877 RM0430 Universal synchronous asynchronous receiver transmitter (USART) Table 153. Error calculation for programmed baud rates at f = 42 MHz or f = 84 Hz, PCLK PCLK (1)(2) oversampling by 16 (continued) Oversampling by 16 (OVER8=0) Baud rate = 42 MHz = 84 MHz PCLK PCLK...
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Page 878: Usart Receiver Tolerance To Clock Deviation
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Table 154. Error calculation for programmed baud rates at f = 42 MHz or f = 84 MHz, PCLK PCLK (1)(2) oversampling by 8 (continued) Oversampling by 8 (OVER8=1) Baud rate = 42 MHz = 84 MHz PCLK PCLK... -
Page 879: Multiprocessor Communication
RM0430 Universal synchronous asynchronous receiver transmitter (USART) The USART receiver tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices: • 10- or 11-bit character length defined by the M bit in the USART_CR1 register •... -
Page 880: Figure 287. Mute Mode Using Idle Line Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Idle line detection (WAKE=0) The USART enters mute mode when the RWU bit is written to 1. It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register. -
Page 881: Parity Control
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Figure 288. Mute mode using address mark detection 28.4.7 Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 157. -
Page 882: Lin (Local Interconnection Network) Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0430 sequence (a read from the status register followed by a read or write access to the USART_DR data register). Note: In case of wakeup by an address mark: the MSB bit of the data is taken into account to identify an address but not the parity bit. -
Page 883: Figure 289. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0430 Universal synchronous asynchronous receiver transmitter (USART) detection circuit receives either a ‘1, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown in Figure 289. -
Page 884: Usart Synchronous Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Figure 290. Break detection in LIN mode vs. Framing error detection 28.4.9 USART synchronous mode The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to 1. In synchronous mode, the following bits must be kept cleared: •... -
Page 885: Figure 291. Usart Example Of Synchronous Transmission
RM0430 Universal synchronous asynchronous receiver transmitter (USART) has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. -
Page 886: Single-Wire Half-Duplex Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Figure 293. USART data clock timing diagram (M=1) Figure 294. RX data setup/hold time Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter for more details. 28.4.10 Single-wire half-duplex communication The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3... -
Page 887: Smartcard
RM0430 Universal synchronous asynchronous receiver transmitter (USART) As soon as HDSEL is written to 1: • the TX and RX lines are internally connected • the RX pin is no longer used • the TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. -
Page 888: Figure 296. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0430 shifting on the next baud clock edge. In Smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. • If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. -
Page 889: Irda Sir Endec Block
RM0430 Universal synchronous asynchronous receiver transmitter (USART) prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 28.4.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: •... -
Page 890: Figure 297. Irda Sir Endec- Block Diagram
Universal synchronous asynchronous receiver transmitter (USART) RM0430 IrDA low-power mode Transmitter: In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz <... -
Page 891: Continuous Communication Using Dma
RM0430 Universal synchronous asynchronous receiver transmitter (USART) 28.4.13 Continuous communication using DMA The USART is capable of continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. -
Page 892: Figure 299. Transmission Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Figure 299. Transmission using DMA Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received. -
Page 893: Hardware Flow Control
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Figure 300. Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. An interrupt will be generated if the interrupt enable flag is set. -
Page 894: Figure 302. Rts Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0430 RTS flow control If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame. -
Page 895: Usart Interrupts
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Note: Special behavior of break frames: when the CTS flow is enabled, the transmitter does not check the nCTS input state to send a break. 28.5 USART interrupts Table 158. USART interrupt requests Interrupt event Event flag Enable control bit... -
Page 896: Usart Registers
Universal synchronous asynchronous receiver transmitter (USART) RM0430 Figure 304. USART interrupt mapping diagram 28.6 USART registers Refer to for a list of abbreviations used in register descriptions. Section 1.1 on page 51 The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 28.6.1 Status register (USART_SR) Address offset: 0x00... - Page 897 RM0430 Universal synchronous asynchronous receiver transmitter (USART) Bits 31:10 Reserved, must be kept at reset value Bit 9 CTS: CTS flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software (by writing it to 0).
- Page 898 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Bit 3 ORE: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
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Page 899: Data Register (Usart_Dr)
RM0430 Universal synchronous asynchronous receiver transmitter (USART) 28.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. -
Page 900: Control Register 1 (Usart_Cr1)
Universal synchronous asynchronous receiver transmitter (USART) RM0430 28.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVER8 Res. WAKE PEIE TXEIE TCIE RXNEIE IDLEIE Bits 31:16 Reserved, must be kept at reset value... - Page 901 RM0430 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever PE=1 in the USART_SR register Bit 7 TXEIE: TXE interrupt enable This bit is set and cleared by software.
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Page 902: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0430 28.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res. -
Page 903: Control Register 3 (Usart_Cr3)
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin 1: The clock pulse of the last data bit is output to the SCLK pin Note: 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected... - Page 904 Universal synchronous asynchronous receiver transmitter (USART) RM0430 Bit 9 CTSE: CTS enable 0: CTS hardware flow control disabled 1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then the transmission is completed before stopping.
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Page 905: Guard Time And Prescaler Register (Usart_Gtpr)
RM0430 Universal synchronous asynchronous receiver transmitter (USART) Bit 0 EIE: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register). -
Page 906: Usart Register Map
Universal synchronous asynchronous receiver transmitter (USART) RM0430 28.6.8 USART register map The table below gives the USART register map and reset values. Table 159. USART register map and reset values Offset Register USART_SR 0x00 Reset value USART_DR DR[8:0] 0x04 Reset value DIV_Fraction USART_BRR DIV_Mantissa[15:4]... - Page 907 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software. SPI mode is selected by default after a device reset.
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Page 908: Spi Extended Features
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.1.2 SPI extended features • SPI TI mode support 29.1.3 I2S features • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •... -
Page 909: Spi Functional Description
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3 SPI functional description 29.3.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the following block diagram Figure 305. -
Page 910: Communications Between One Master And One Slave
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management). -
Page 911: Figure 307. Half-Duplex Single Master/ Single Slave Application
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 307. Half-duplex single master/ single slave application 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and slave. - Page 912 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 308. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
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Page 913: Standard Multi-Slave Communication
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.3 Standard multi-slave communication In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave (see Figure 309.). The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input. -
Page 914: Multi-Master Communication
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.4 Multi-master communication Unless SPI bus is not designed for a multi-master capability primarily, the user can use build in feature which detects a potential conflict between two nodes trying to master the bus at the same time. -
Page 915: Figure 311. Hardware/Software Slave Select Management
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) – NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the MCU is set as master. The NSS pin is managed by the hardware. The NSS signal is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept low until the SPI is disabled (SPE =0). -
Page 916: Communication Formats
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.6 Communication formats During SPI communication, receive and transmit operations are performed simultaneously. The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines. The communication format depends on the clock phase, the clock polarity and the data frame format. -
Page 917: Figure 312. Data Clock Timing Diagram
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 312. Data clock timing diagram Note: The order of data bits depends on LSBFIRST bit setting. Data frame format The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the value of the LSBFIRST bit. -
Page 918: Spi Configuration
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.3.7 SPI configuration The configuration procedure is almost the same for master and slave. For specific mode setups, follow the dedicated chapters. When a standard communication is to be initialized, perform these steps: Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins. -
Page 919: Data Transmission And Reception Procedures
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.3.9 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while in transmission, data are first stored into an internal Tx buffer before being transmitted. A read access to the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer. -
Page 920: Figure 313. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 always transacted and processed by the master even if the slave cannot not prepare them correctly in time. It is preferable for the slave to use DMA, especially when data frames are shorter and bus rate is high. Each sequence must be encased by the NSS pulse in parallel with the multislave system to select just one of the slaves for communication. -
Page 921: Procedure For Disabling The Spi
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 314. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers 29.3.10 Procedure for disabling the SPI When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. -
Page 922: Communication Using Dma (Direct Memory Addressing)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Note: During discontinuous communications, there is a 2 APB clock period delay between the write operation to the SPI_DR register and BSY bit setting. As a consequence it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data. -
Page 923: Figure 315. Transmission Using Dma
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) To close communication it is mandatory to follow these steps in order: Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used. Disable the SPI by following the SPI disable procedure. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the SPI_CR2 register, if DMA Tx and/or DMA Rx are used. -
Page 924: Spi Status Flags
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 316. Reception using DMA 29.3.12 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, the TXE flag indicates that the Tx buffer is empty and that the next data to be transmitted can be loaded into the buffer. -
Page 925: Spi Error Flags
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) The BSY flag is cleared under any one of the following conditions: • When the SPI is correctly disabled • When a fault is detected in Master mode (MODF bit set to 1) •... -
Page 926: Spi Special Features
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 CRC error (CRCERR) This flag is used to verify the validity of the value received when the CRCEN bit in the SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value received in the shift register does not match the receiver SPIx_RXCRC value. -
Page 927: Crc Calculation
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt (ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupts are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set. - Page 928 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The received CRC is stored in the Rx buffer like any other data frame. A CRC-format transaction takes one more data frame to communicate at the end of data sequence. When the last CRC data is received, an automatic check is performed comparing the received value and the value in the SPIx_RXCRC register.
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Page 929: Spi Interrupts
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) has to be reset between sessions by the SPI disable sequence by re-enabling the CRCEN bit described above at both master and slave sides, else the CRC calculation can be corrupted at this specific mode. 29.5 SPI interrupts During SPI communication an interrupts can be generated by the following events:... -
Page 930: Supported Audio Protocols
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.6 S functional description 29.6.1 S general description The block diagram of the I S is shown in . The SPI can function as an audio I S interface when the I S capability is enabled (by setting the I2SMOD bit in the SPIx_I2SCFGR register). - Page 931 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only one read/write operation).
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Page 932: Figure 320. Transmitting 0X8Eaa33
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 • In transmission mode: If 0x8EAA33 has to be sent (24-bit): Figure 320. Transmitting 0x8EAA33 • In reception mode: If data 0x8EAA33 is received: Figure 321. Receiving 0x8EAA33 Figure 322. I S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, only one access to the SPIx_DR register is required. -
Page 933: Figure 323. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Figure 323. Example of 16-bit data frame extended to 32-bit channel frame For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware. -
Page 934: Figure 326. Msb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 326. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 LSB justified standard This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit full-accuracy frame formats). -
Page 935: Figure 329. Operations Required To Transmit 0X3478Ae
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register are required by software or by DMA. The operations are shown below. Figure 329. Operations required to transmit 0x3478AE •... -
Page 936: Figure 332. Example Of 16-Bit Data Frame Extended To 32-Bit Channel Frame
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Figure 332. Example of 16-bit data frame extended to 32-bit channel frame In transmission mode, when a TXE event occurs, the application has to write the data to be transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit). The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD. -
Page 937: Clock Generator
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data (and so two synchronization signals) needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in slave mode. - Page 938 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the desired frequency, the linear divider needs to be programmed according to the formulas below: When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):...
- Page 939 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) A full frame has to be considered as a left channel data transmission followed by a right channel data transmission. It is not possible to have a partial frame where only the left channel is sent.
- Page 940 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 • For all other combinations of DATLEN and CHLEN, whatever the audio mode selected through the I2SSTD bits, carry out the following sequence to switch off the I Wait for the second to last RXNE = 1 (n – 1) Then wait one I S clock cycle (using a software loop) Disable the I...
- Page 941 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR register with the next data to transmit before the end of the current transmission. An underrun flag is set and an interrupt may be generated if the data are not written into the SPIx_DR register before the first clock edge of the next data communication.
- Page 942 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 The BSY flag is cleared: • When a transfer completes (except in master transmit mode, in which the communication is supposed to be continuous) • When the I S is disabled When communication is continuous: •...
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Page 943: Dma Features
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Overrun flag (OVR) This flag is set when data are received and the previous data have not yet been read from the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated if the ERRIE bit is set in the SPIx_CR2 register. - Page 944 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.7 SPI and I S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition by can be accessed by 8-bit access. Refer to Section 1.1 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
- Page 945 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 11 DFF: Data frame format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. It is not used in I S mode.
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Page 946: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing. -
Page 947: Spi Status Register (Spi_Sr)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the cell can work in multimaster configuration 1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work in a multimaster environment. - Page 948 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bit 5 MODF: Mode fault 0: No mode fault occurred 1: Mode fault occurred This flag is set by hardware and reset by a software sequence. Refer to Section 29.4 on page 926 for the software sequence.
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Page 949: Spi Data Register (Spi_Dr)
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.7.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer). - Page 950 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 29.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
- Page 951 RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.7.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 PCMSY Res. Res. Res. Res. I2SMOD I2SE I2SCFG I2SSTD CKPOL DATLEN CHLEN Bits 15: Reserved, must be kept at reset value. Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected...
- Page 952 Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0430 Bit 3 CKPOL: Steady state clock polarity 0: I S clock steady state is low level 1: I S clock steady state is high level Note: For correct operation, this bit should be configured when the I S is disabled.
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Page 953: Spi Register Map
RM0430 Serial peripheral interface/ inter-IC sound (SPI/I2S) 29.7.10 SPI register map The table provides shows the SPI register map and reset values. Table 162. SPI register map and reset values Offset Register SPI_CR1 [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 0x04 Reset value... -
Page 954: Serial Audio Interface (Sai)
Serial audio interface (SAI) RM0430 Serial audio interface (SAI) 30.1 Introduction The SAI interface (serial audio interface) offers a wide set of audio protocols due to its flexibility and wide range of configurations. Many stereo or mono audio applications may be targeted. -
Page 955: Main Features
RM0430 Serial audio interface (SAI) 30.2 Main features • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. •... -
Page 956: Figure 337. Functional Block Diagram
Serial audio interface (SAI) RM0430 Figure 337. Functional block diagram The SAI is mainly composed of two audio sub-blocks with their own clock generator. Each audio block integrates a 32-bit shift register controlled by their own functional state machine. Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by DMA in order to leave the CPU free during the communication. -
Page 957: Main Sai Modes
RM0430 Serial audio interface (SAI) 30.4 Main SAI modes Each audio sub-block of the SAI can be configured to be master or slave via bit MODE[0] in the SAI_xCR1 register of the selected audio block. In master mode: • The bit clock is generated by the SAI using the clock generator on pin SCK_A or SCK_B (depending which audio block is declared as a master in the SAI). -
Page 958: Sai Synchronization Mode
Serial audio interface (SAI) RM0430 30.5 SAI synchronization mode Internal synchronization An audio block can be declared synchronous with the second audio block. In this case, the bit clock and the frame synchronization signals are shared to reduce the number of external pins used for the communication. -
Page 959: Frame Length
RM0430 Serial audio interface (SAI) In AC’97 mode (bit PRTCFG[1:0] = 10 in the SAI_xCR1 register), the frame synchronization shape is forced to be configured to target these protocols. The SAI_xFRCR register value is ignored. Each audio block is independent and so each requires a specific configuration. 30.7.1 Frame length •... -
Page 960: Frame Synchronization Active Level Length
Serial audio interface (SAI) RM0430 described in Section 30.13), but there will be no interruption in the audio communication flow. 30.7.3 Frame synchronization active level length Bit FSALL[6:0] in the SAI_xFRCR register configures the length of the active level of the Frame synchronization signal. -
Page 961: Slot Configuration
RM0430 Serial audio interface (SAI) Figure 339. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) 1. The frame length should be even. If bit FSDEF in SAI_xFRCR is kept clear, so FS signal is equivalent to a start of frame, and if the number of slots defined in bit NBSLOT[3:0] in SAI_xSLOTR multiplied by the number of bits by slot configured in bit SLOTSZ[1:0] in SAI_xSLOTR is less than the frame size (bit FRL[7:0] in the SAI_xFRCR register), then,... -
Page 962: Figure 341. Slot Size Configuration With Fboff = 0 In Sai_Xslotr
Serial audio interface (SAI) RM0430 Each slot can be defined as a valid slot, or not, by setting bit SLOTEN[15:0] in the SAI_xSLOTR register. In an audio frame, during the transfer of a non-valid slot, 0 value will be forced on the data line or the SD data line will be released to HI-z (refer to Section 30.12.4) if the audio block is transmitter, or the received value from the end of this slot will be ignored. -
Page 963: Sai Clock Generator
RM0430 Serial audio interface (SAI) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: FBOFF ≤ (SLOTSZ - DS), DS ≤ SLOTSZ, NBSLOT x SLOTSZ ≤ FRL (frame length), The number of slots should be even when bit FSDEF in the SAI_xFRCR register is set. In AC’97 (bit PRTCFG[1:0] = 10), the slot size is automatically set as defined in Section 30.11. -
Page 964: Internal Fifos
Serial audio interface (SAI) RM0430 Table 163. Example of possible audio frequency sampling range Input SAI_CK_x clock Most usual audio frequency MCKDIV[3:0] frequency sampling achievable 192 kHz MCKDIV[3:0] = 0000 96 kHz MCKDIV[3:0] = 0001 192 kHz x 256 48 kHz MCKDIV[3:0] = 0010 16 kHz MCKDIV[3:0] = 0100... - Page 965 RM0430 Serial audio interface (SAI) An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on: • FIFO threshold setting (FLTH bits in SAI_CR2) • Communication direction transmitter or receiver (see Section : Interrupt generation in transmitter mode Section : Interrupt generation in reception mode)
- Page 966 Serial audio interface (SAI) RM0430 (FLTH[2:0] bits in SAI_xSR is higher or equal to 010b). This Interrupt (FREQ bit in SAI_XSR register) is cleared by hardware when less than a quarter of the FIFO data locations become available (FLTH[2:0] bits in SAI_xSR is less than 010b). •...
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Page 967: Ac'97 Link Controller
RM0430 Serial audio interface (SAI) 30.11 AC’97 link controller The SAI is able to work as an AC’97 link controller. In this protocol: • The slot number and the slot size are fixed. • The frame synchronization signal is perfectly defined and has a fixed shape. To select this protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10. -
Page 968: Mute Mode
Serial audio interface (SAI) RM0430 30.12.1 Mute mode Mute mode may be used when the audio block is a transmitter or receiver. Transmitter In transmitter mode, Mute mode can be selected at anytime. Mute mode is active for entire audio frames. The bit MUTE in the SAI_xCR2 register requests Mute mode when it is set during an on-going frame. -
Page 969: Companding Mode
RM0430 Serial audio interface (SAI) 30.12.3 Companding mode Telecommunication applications may require to process the data to transmit or to receive with a data companding algorithm. Depending on the COMP[1:0] bit in the SAI_xCR2 register (used only when TDM mode is selected), the software may choose to process or not the data before sending it on SD serial output line (compression) or to expand the data after the reception on SD serial input line (expansion) as illustrated in... -
Page 970: Output Data Line Management On An Inactive Slot
Serial audio interface (SAI) RM0430 30.12.4 Output data line management on an inactive slot In transmitter mode, it is possible to choose the behavior of the SD line in output when an inactive slot is sent on the data line (via bit TRIS in the SAI_xCR2 register when the SAI is disabled). -
Page 971: Figure 346. Tristate Strategy On Sd Output Line On An Inactive Slot
RM0430 Serial audio interface (SAI) Figure 346. Tristate strategy on SD output line on an inactive slot When the selected audio protocol uses the FS signal as a start of frame and a channel side identification (bit FSDEF = 1 in the SAI_xFRCR register), the tristate mode is managed according to Figure 347 (where bit TRIS in the SAI_xCR1 register = 1, and FSDEF=1, and... - Page 972 Serial audio interface (SAI) RM0430 Figure 347. Tristate on output data line in a protocol like I2S If the TRIS bit in the SAI_xCR2 register is cleared, all the High impedance states on the SD output line on Figure 346 Figure 347 are replaced by a drive with a value of 0.
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Page 973: Figure 348. Overrun Detection Error
RM0430 Serial audio interface (SAI) was stored internally when the overrun condition was detected, and this, to avoid data slot de-alignment in the destination memory (refer to Figure 348). The OVRUDR flag is cleared when bit COVRUDR is set in the SAI_xCLRFR register. Figure 348. -
Page 974: Anticipated Frame Synchronisation Detection (Afsdet)
Serial audio interface (SAI) RM0430 Figure 349. FIFO underrun event 30.13.2 Anticipated frame synchronisation detection (AFSDET) This flag AFSDET is used only in Slave mode. In master mode, it is never asserted. It informs about the detection of a frame synchronisation (FS) earlier than expected since the frame length, the frame polarity, the frame offset are defined and known. -
Page 975: Codec Not Ready (Cnrdy Ac'97)
RM0430 Serial audio interface (SAI) The late frame synchronisation detection flag is set when the error is detected, SAI needs to be resynchronized with the master (the four steps described above should be respected). This detection and flag assertion can detect glitches on the SCK clock in a noisy environment, detected by the state machine of the audio block. -
Page 976: Disabling The Sai
Serial audio interface (SAI) RM0430 Table 164. Interrupt sources Interru Interrupt Audio block mode Interrupt enable Interrupt clear source group Depend on: - FIFO threshold setting (FLTH bits in SAI_CR2) Master or Slave FREQIE in FREQ FREQ - Communication direction SAI_xIM register Receiver or transmitter transmitter or receiver... -
Page 977: Sai Dma Interface
RM0430 Serial audio interface (SAI) 30.16 SAI DMA interface In order to free the CPU and to optimize the bus bandwidth, each SAI audio block has an independent DMA interface in order to read or to write into the SAI_xDR register (to hit the internal FIFO). -
Page 978: Sai Registers
Serial audio interface (SAI) RM0430 30.17 SAI registers 30.17.1 SAI xConfiguration register 1 (SAI_xCR1) where x is A or B Address offset: Block A: 0x004 Address offset: Block B: 0x024 Reset value: 0x0000 0040 MCKDIV[3:0] NODIV DMAEN SAIxEN Reserved Res. OutDri LSBFIR MONO... - Page 979 RM0430 Serial audio interface (SAI) Bit 12 MONO: Mono mode. This bit is set and cleared by software. 0: Stereo mode 1: Mono mode. This bit has a meaning only when the number of slots is equal to 2. When the Mono mode is selected, the data of the slot 0 data is duplicated on the slot 1 when the audio block is a transmitter.
- Page 980 Serial audio interface (SAI) RM0430 Bit 4 Reserved, always read as 0. Bits 3:2 PRTCFG[1:0]: Protocol configuration. These bits are set and cleared by software. 00: Free protocol 01: Not used 10: AC’97 protocol 11: Not used Free protocol selection allows to use the powerful configuration of the audio block to address a specific audio protocol (like I2S, LSB/MSB justified, TDM, PCM/DSP...) setting most of the configuration register bits as well as frame configuration register.
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Page 981: Sai Xconfiguration Register 2 (Sai_Xcr2) Where X Is A Or B
RM0430 Serial audio interface (SAI) 30.17.2 SAI xConfiguration register 2 (SAI_xCR2) where x is A or B Address offset: Block A: 0x008 Address offset: Block B: 0x028 Reset value: 0x0000 0000 Reserved MUTE COMP[1:0] MUTECNT[5:0] Mute TRIS FFLUS Bits 31:16 Reserved, always read as 0 Bits 15:14 COMP[1:0]: Companding mode. - Page 982 Serial audio interface (SAI) RM0430 Bit 6 MUTEVAL: Mute value. This bit is set and cleared by software.This bit has to be written before enabling the audio block: SAIxEN. 0: Bit value 0 is sent during the MUTE mode. 1: Last values are sent during the MUTE mode. This bit has a meaning only when the audio block is a transmitter and when the number of slots is lower or equal to 2 and if the MUTE bit is set.
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Page 983: Sai Xframe Configuration Register (Sai_Xfrcr) Where X Is A Or B
RM0430 Serial audio interface (SAI) 30.17.3 SAI xFrame configuration register (SAI_XFRCR) where x is A or B Address offset: Block A: 0x00C Address offset: Block B: 0x02C Reset value: 0x0000 0007 Note: This register has no meaning in AC’97 audio protocol FSOFF FSPOL FSDEF Reserved FSALL[6:0]... - Page 984 Serial audio interface (SAI) RM0430 Bit 15 Reserved, always read as 0. Bits 14:8 FSALL[6:0]: Frame synchronization active level length. These bits are set and cleared by software The value set in these bits specifies the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits have no meaning and are not used in AC’97 audio block configuration.
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Page 985: Sai Xslot Register (Sai_Xslotr) Where X Is A Or B
RM0430 Serial audio interface (SAI) 30.17.4 SAI xSlot register (SAI_xSLOTR) where x is A or B Address offset: Block A: 0x010 Address offset: Block B: 0x030 Reset value: 0x0000 0000 Note: This register has no meaning in AC’97 audio protocol SLOTEN[15:0] NBSLOT[3:0] SLOTSZ[1:0]... -
Page 986: Sai Xinterrupt Mask Register2(Sai_Xim) Where X Is A Or B
Serial audio interface (SAI) RM0430 30.17.5 SAI xInterrupt mask register2(SAI_xIM) where x is A or B Address offset: blockA: 0x014 Address offset: block B: 0x034 Reset value: 0x0000 0000 Reserved LFSDETI AFSDET CNRDY FREQI WCKC OVRU EDET FGIE DRIE Reserved Bits 31:7 Reserved, always read as 0. - Page 987 RM0430 Serial audio interface (SAI) Bit 2 WCKCFGIE: Wrong clock configuration interrupt enable. This bit is set and cleared by software. 0: Interrupt is disabled 1: Interrupt is enabled This bit is considered only if the audio block is configured as master (MODE[1] = 0 in the SAI_ACR1 register) and bit NODIV = 0 in the SAI_xCR1 register.
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Page 988: Sai Xstatus Register (Sai_Xsr) Where X Is A Or B
Serial audio interface (SAI) RM0430 30.17.6 SAI xStatus register (SAI_xSR) where x is A or B Address offset: block A: 0x018 Address offset: block B: 0x038 Reset value: 0x0000 0008 FLTH Reserved MUTED LFSDET AFSDET CNRDY FREQ WCKCFG OVRUDR Reserved Bits 31:19 Reserved, always read as 0. - Page 989 RM0430 Serial audio interface (SAI) Bit 4 CNRDY: Codec not ready. This bit is read only. 0: The external AC’97 codec is ready 1: The external AC’97 codec is not ready This bit is used only when the AC’97 audio protocol is selected in the SAI_xCR1 register and is configured in receiver mode.
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Page 990: Sai Xclear Flag Register (Sai_Xclrfr) Where X Is A Or B
Serial audio interface (SAI) RM0430 30.17.7 SAI xClear flag register (SAI_xCLRFR) where X is A or B Address offset: block A: 0x01C Address offset: block B: 0x03C Reset value: 0x0000 0000 Reserved CAFSDE CMUTE COVRUD CLFSDET CCNRDY CWCKCFG Reserved Reserved Bits 31:7 Reserved, always read as 0. -
Page 991: Sai Xdata Register (Sai_Xdr) Where X Is A Or B
RM0430 Serial audio interface (SAI) 30.17.8 SAI xData register (SAI_xDR) where x is A or B Address offset: block A: 0x020 Address offset: block B: 0x040 Reset value: 0x0000 0000 DATA[31:16] DATA[15:0] Bits 31:0 DATA[31:0]: Data A write into this register has the effect of loading the FIFO if the FIFO is not full. A read from this register has to effect of draining-up the FIFO if the FIFO is not empty. - Page 992 Serial audio interface (SAI) RM0430 Table 165. SAI register map and reset values (continued) Register Offset and reset value 0x0014 SAI_xIM 0x003 Reset value 0x0018 SAI_xSR 0x003 0 0 0 Reset value 0x001 SAI_xCLRF 0x003 Reset value DATA[31:0] 0x0020 SAI_xDR 0x004 0 0 0 0 0 0 0 0 Reset value...
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Page 993: Secure Digital Input/Output Interface (Sdio)
RM0430 Secure digital input/output interface (SDIO) Secure digital input/output interface (SDIO) 31.1 SDIO main features The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The MultiMediaCard system specifications are available through the MultiMediaCard Association website, published by the MMCA technical committee. -
Page 994: Figure 350. "No Response" And "No Data" Operations
Secure digital input/output interface (SDIO) RM0430 Figure 350. “No response” and “no data” operations Figure 351. (Multiple) block read operation Figure 352. (Multiple) block write operation Note: The SDIO will not send any data as long as the Busy signal is asserted (SDIO_D0 pulled low). -
Page 995: Sdio Functional Description
RM0430 Secure digital input/output interface (SDIO) Figure 353. Sequential read operation Figure 354. Sequential write operation 31.3 SDIO functional description The SDIO consists of two parts: • The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. -
Page 996: Table 166. Sdio I/O Definitions
Secure digital input/output interface (SDIO) RM0430 By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used. -
Page 997: Sdio Adapter
RM0430 Secure digital input/output interface (SDIO) 31.3.1 SDIO adapter Figure 356 shows a simplified block diagram of an SDIO adapter. Figure 356. SDIO adapter The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits: •... -
Page 998: Figure 357. Control Unit
Secure digital input/output interface (SDIO) RM0430 Figure 357. Control unit The control unit is illustrated in Figure 357. It consists of a power management subunit and a clock management subunit. The power management subunit disables the card bus output signals during the power-off and power-up phases. -
Page 999: Figure 359. Sdio Adapter Command Path
RM0430 Secure digital input/output interface (SDIO) Command path The command path unit sends commands to and receives responses from the cards. Figure 359. SDIO adapter command path • Command path state machine (CPSM) – When the command register is written to and the enable bit is set, command transfer starts. -
Page 1000: Figure 360. Command Path State Machine (Sdio)
Secure digital input/output interface (SDIO) RM0430 Figure 360. Command path state machine (SDIO) When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered.
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