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RM0090
Figure 25. System implementation of the two DMA controllers
(STM32F405xx/07xx and STM32F415xx/17xx)
DMA controller 2
DMA controller 1
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case of the DMA2 controller, thus
only DMA2 streams are able to perform memory-to-memory transfers.
DMA request
MAPPING
Doc ID 018909 Rev 4
DCODE
Bus matrix
(AHB
ICODE
multilayer)
AHB-APB
bridge2
(dual AHB)
AHB-APB
bridge1
(dual AHB)
DMA controller (DMA)
Flash
memory
112 KB SRAM
16 KB SRAM
AHB1 peripherals
APB2
APB2
peripherals
APB1
APB1
peripherals
AHB2 peripherals
External memory
controller (FSMC)
MS19927V2
216/1422
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