Des/Tdes Cryptographic Core; Figure 202. Block Diagram (Stm32F42Xxx And Stm32F43Xxx) - ST STM32F40 Series Reference Manual

Cryptographic processor (CRYP)

Figure 202. Block diagram (STM32F42xxx and STM32F43xxx)

Status
CRYP_SR
DMA control register
CRYP_DMACR
Interrupt registers
CRYP_IMSCR
CRYP_RIS
CRYP_MISR
Control register
CRYP_CR
Initialization vectors
CRYP_IV0...IV1
Key
CRYP_K0. ..K3
20.3.1

DES/TDES cryptographic core

The DES/Triple-DES cryptographic core consists of three components:
●
The DES algorithm (DEA)
● Multiple keys (1 for the DES algorithm, 1 to 3 for the TDES algorithm)
●
The initialization vector (used in the CBC mode)
The basic processing involved in the TDES is as follows: an input block is read in the DEA
and encrypted using the first key, K1 (K0 is not used in TDES mode). The output is then
decrypted using the second key, K2, and encrypted using the third key, K3. The key
depends on the algorithm which is used:
●
DES mode: Key = [K1]
●
TDES mode: Key = [K3 K2 K1]
where Kx=[KxR KxL], R = right, L = left
According to the mode implemented, the resultant output block is used to calculate the
ciphertext.
Note that the outputs of the intermediate DEA stages is never revealed outside the
cryptographic boundary.
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32-bit AHB2 bus
CRYP_DIN
8 × 32-bit
IN FIFO
swappi ng
IV0...IV127
k255...k0
Doc ID 018909 Rev 4
CRYP_DOUT
8 × 32-bit
OUT FIFO
swappin g
DES/TDES/AES
Processor core
RM0090
Context swapping
CRYP_CSGCMCCM0..7
CRYP_CSGCM0..7
MS30441V1