Control Register 2 (Usart_Cr2) - ST STM32F40 Series Reference Manual

RM0090
26.6.5

Control register 2 (USART_CR2)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
15 14 13
LINEN STOP[1:0]
Res.
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Bits 31:15 Reserved, must be kept at reset value
Bit 14 LINEN: LIN mode enable
This bit is set and cleared by software.
0: LIN mode disabled
1: LIN mode enabled
The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in
the USART_CR1 register, and to detect LIN Sync breaks.
Bits 13:12 STOP: STOP bits
These bits are used for programming the stop bits.
00: 1 Stop bit
01: 0.5 Stop bit
10: 2 Stop bits
11: 1.5 Stop bit
Note: The 0.5 Stop bit and 1.5 Stop bit are not available for UART4 & UART5.
Bit 11 CLKEN: Clock enable
This bit allows the user to enable the SCLK pin.
0: SCLK pin disabled
1: SCLK pin enabled
This bit is not available for UART4 & UART5.
Bit 10 CPOL: Clock polarity
This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous
mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship
0: Steady low value on SCLK pin outside transmission window.
1: Steady high value on SCLK pin outside transmission window.
This bit is not available for UART4 & UART5.
Bit 9 CPHA: Clock phase
This bit allows the user to select the phase of the clock output on the SCLK pin in synchronous
mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see
figures
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: This bit is not available for UART4 & UART5.
Universal synchronous asynchronous receiver transmitter (USART)
28 27 26 25
12 11 10 9
CLKEN CPOL CPHA
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258 to 259)
Doc ID 018909 Rev 4
24 23 22 21
Reserved
8 7 6 5
LBCL Res. LBDIE LBDL
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20 19 18 17
4 3 2 1
Res. ADD[3:0]
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16
0
rw
788/1422