Adc Injected Channel Data Offset Register X (Adc_Jofrx)(X=1; Adc Watchdog Higher Threshold Register (Adc_Htr); Adc Watchdog Lower Threshold Register (Adc_Ltr) - ST STM32F40 Series Reference Manual

RM0090
11.13.6

ADC injected channel data offset register x (ADC_JOFRx)(x=1..4)

Address offset: 0x14-0x20
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
11.13.7

ADC watchdog higher threshold register (ADC_HTR)

Address offset: 0x24
Reset value: 0x0000 0FFF
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
11.13.8

ADC watchdog lower threshold register (ADC_LTR)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
27 26 25
11 10 9
rw rw rw
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
27 26 25
11 10 9
rw rw rw
27 26 25
11 10 9
rw rw rw
Doc ID 018909 Rev 4
Analog-to-digital converter (ADC)
24 23 22 21
Reserved
8 7 6 5
JOFFSETx[11:0]
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
HT[11:0]
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24 23 22 21
Reserved
8 7 6 5
LT[11:0]
rw rw rw rw
20 19 18 17
4 3 2 1
rw rw rw rw
20 19 18 17
4 3 2 1
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20 19 18 17
4 3 2 1
rw rw rw rw
16
0
rw
16
0
rw
16
0
rw
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