Flash Option Control Register (Flash_Optcr) - ST STM32F40 Series Reference Manual

RM0090
Bit 2 MER: Mass Erase of bank 1 sectors
Bit 1 SER: Sector Erase
Bit 0 PG: Programming
3.8.7

Flash option control register (FLASH_OPTCR)

The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31 30 29
Reserved
15 14 13
rw rw rw
Bits 31:28 Reserved, must be kept cleared.
Bits 27:16 nWRP: Not write protect
These bits contain the value of the write-protection option bytes of sectors after reset. They
can be written to program a new write protect value into Flash memory.
0: Write protection active on selected sector
1: Write protection not active on selected sector
Bits 15:8 RDP: Read protect
These bits contain the value of the read-protection option level after reset. They can be
written to program a new read protection value into Flash memory.
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bits 7:5 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to
program a new user option byte value into Flash memory.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
Note: When changing the WDG mode from hardware to software or from software to
Bit 4 Reserved, must be kept cleared.
Erase activated of bank 1 sectors.
Sector Erase activated.
Flash programming activated.
28 27 26 25
rw rw rw
12 11 10 9
RDP[7:0]
rw rw rw rw
hardware, a system reset is required to make the change effective.
Doc ID 018909 Rev 4
Embedded Flash memory interface
24 23 22 21
nWRP[11:0]
rw rw rw rw
8 7 6 5
nRST_ nRST_ WDG_
STDBY STOP SW
rw rw rw rw
20 19 18
rw rw rw
4 3 2
OPTST
BOR_LEV
Reserv
ed
rw rw
17 16
rw rw
1 0
OPTLO
RT CK
rs rs
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