ST STM32F40 Series Reference Manual page 54

RM0090
Table 2. STM32F4xx register boundary addresses (continued)
Boundary address
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2000 - 0x4001 23FF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Peripheral
SPI1
SDIO
ADC1 - ADC2 - ADC3
USART6
USART1
TIM8
TIM1
UART8
UART7
DAC
PWR
CAN2
CAN1
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
APB1
I2S2ext
IWDG
WWDG
RTC & BKP Registers
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
Doc ID 018909 Rev 4
Bus
Section 27.5.10: SPI register map on page 845
Section 28.9.16: SDIO register map on page 901
Section 11.13.18: ADC register map on page 307
APB2
Section 26.6.8: USART register map on page 793
Section 14.4.21: TIM1&TIM8 register map on
page 420
APB1 Section 26.6.8: USART register map on page 793
Section 12.5.15: DAC register map on page 329
Section 5.5: PWR register map on page 109
Section 24.9.5: bxCAN register map on page 705
Section 25.6.11: I2C register map on page 741
Section 26.6.8: USART register map on page 793
Section 27.5.10: SPI register map on page 845
Section 18.4.5: IWDG register map on page 540
Section 19.6.4: WWDG register map on page 547
Section 23.6.21: RTC register map on page 662
Section 16.6.11: TIM10/11/13/14 register map on
page 524
Section 16.5.14: TIM9/12 register map on
page 514
Section 17.4.9: TIM6&TIM7 register map on
page 535
Section 15.4.21: TIMx register map on page 480
Memory and bus architecture
Register map
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