Figure 265. Transmission Using Dma - ST STM32F40 Series Reference Manual

RM0090

Figure 265. Transmission using DMA

Idle preamble
TX line
TXE flag
DMA request
USART_DR
F1
TC flag
DMA writes
USART_DR
flag DMA TCIF
(Transfer complete)
software configures DMA writes F1
the DMA to send 3 into
data and enables the USART_DR
USART
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_DR register to a SRAM area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for USART reception, use the following procedure:
1. Write the USART_DR register address in the DMA control register to configure it as the
source of the transfer. The data will be moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data will be loaded from USART_DR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred in the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector. The DMAR bit should
be cleared by software in the USART_CR3 register during the interrupt subroutine.
Note: If DMA is used for reception, do not enable the RXNEIE bit.
Universal synchronous asynchronous receiver transmitter (USART)
Frame 1
set by hardware
cleared by DMA read
F2
set by hardware
DMA writes F2 DMA writes F3 The DMA transfer
into into
USART_DR USART_DR.
Doc ID 018909 Rev 4
Frame 2
set by hardware
cleared by DMA read
F3
clear
by software
is complete
(TCIF=1 in
DMA_ISR)
Frame 3
set by hardware
ignored by the DMA
because DMA transfer is complete
software waits until TC=1
set
by hardware
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