Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr) - ST STM32F40 Series Reference Manual

RM0090
Bits 27:15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO
Caution: The software has to set these bits correctly to ensure that the VCO output
Bits 5:0 Reserved, must be kept at reset value.
6.3.31

RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)

This register is available only on STM32F42xxx and STM32F43xxx devices.
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
Reserved
15 14 13 12
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TIMPRE: Timers clocks prescalers selection
Bits 23: 0 Reserved, must be kept at reset value.
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to
write these bits.
frequency is between 192 and 432 MHz.
VCO output frequency = VCO input frequency × PLLI2SN with 192 ≤ PLLI2SN ≤ 432
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration
...
011000000: PLLI2SN = 192
011000001: PLLI2SN = 193
011000010: PLLI2SN = 194
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration
...
111111111: PLLI2SN = 511, wrong configuration
27 26 25
11 10 9
Set and reset by software to control the clock frequency of all the timers connected to APB1
and APB2 domain.
0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, TIMxCLK = PCLKx . Otherwise, the timer clock frequencies are set to
twice to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
1:If the APB prescaler ( PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, 2 or 4, TIMxCLK = HCLK. Otherwise, the timer clock frequencies are set
to four times to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.
Doc ID 018909 Rev 4
24 23 22
TIMPRE
rw
8 7 6
Reserved
Reset and clock control for (RCC)
21 20 19 18
Reserved
5 4 3 2
17 16
1 0
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