ST STM32F40 Series Reference Manual page 838

RM0090
Bit 10 RXONLY: Receive only
Note: Not used in I
Bit 9 SSM: Software slave management
Note: Not used in I
Bit 8 SSI: Internal slave select
Note: Not used in I
Bit 7 LSBFIRST: Frame format
Note: This bit should not be changed when communication is ongoing.
Bit 6 SPE: SPI enable
Note: 1- Not used in I
Note: 2- When disabling the SPI, follow the procedure described in
Bits 5:3 BR[2:0]: Baud rate control
Note: These bits should not be changed when communication is ongoing.
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
Note: This bit should not be changed when communication is ongoing.
This bit combined with the BIDImode bit selects the direction of transfer in 2-line
unidirectional mode. This bit is also useful in a multislave system in which this particular
slave is not accessed, the output from the accessed slave is not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
2
S mode
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
2
S mode and SPI TI mode
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
2
S mode and SPI TI mode
0: MSB transmitted first
1: LSB transmitted first
2
Not used in I S mode and SPI TI mode
0: Peripheral disabled
1: Peripheral enabled
2
S mode.
SPI.
000: f /2100: f /32
PCLK PCLK
001: f /4101: f /64
PCLK PCLK
010: f /8110: f /128
PCLK PCLK
011: f /16111: f
PCLK PCLK
2
Not used in I S mode
0: Slave configuration
1: Master configuration
2
Not used in I S mode
0: CK to 0 when idle
1: CK to 1 when idle
2
Not used in I S mode and SPI TI mode
Doc ID 018909 Rev 4
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Serial peripheral interface (SPI)
Section 27.3.8: Disabling the
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