Debug Mode; Iwdg Registers; Table 85. Min/Max Iwdg Timeout Period At 32 Khz (Lsi); Figure 198. Independent Watchdog Block Diagram - ST STM32F40 Series Reference Manual

Independent watchdog (IWDG)
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
18.3.3

Debug mode

When the microcontroller enters debug mode (Cortex™-M4F core halted), the IWDG
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and

Figure 198. Independent watchdog block diagram

CORE
LSI
Note: The watchdog function is implemented in the V
Stop and Standby modes.
Table 85.
Prescaler divider
/16
/32
/64
/128
/256
1. These timings are given for a 32 kHz clock but the microcontroller's internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
18.4

IWDG registers

Refer to
The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
537/1422
Prescaler register Status register
IWDG_PR IWDG_SR
8-bit
prescaler
V DD voltage domain
Min/max IWDG timeout period at 32 kHz (LSI)
PR[2:0] bits
/4 0
/8 1
2
3
4
5
6
Section 1.1 on page 47
Doc ID 018909 Rev 4
I2C.
Reload register
IWDG_RLR
12-bit reload value
12-bit downcounter
voltage domain that is still functional in
DD
Min timeout (ms) RL[11:0]=
0x000
0.125
0.25
0.5
1
2
4
8
for a list of abbreviations used in register descriptions.
Section 33.16.2: Debug support
Key register
IWDG_KR
IWDG reset
(1)
Max timeout (ms) RL[11:0]=
0xFFF
512
1024
2048
4096
8192
16384
32768
RM0090
MS19944V1