Usb Data Fifos; Peripheral Fifo Architecture; Peripheral Rx Fifo; Figure 363. Device-Mode Fifo Address Mapping And Ahb Fifo Access Mapping - ST STM32F40 Series Reference Manual

USB on-the-go full-speed (OTG_FS)
30.10

USB data FIFOs

The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control
mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space
into Tx-FIFOs into which the application pushes the data to be temporarily stored before the
USB transmission, and into a single Rx FIFO where the data received from the USB are
temporarily stored before retrieval (popped) by the application. The number of instructed
FIFOs and how these are organized inside the RAM depends on the device's role. In
peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO
size is software configured to better meet the application requirements.
30.11

Peripheral FIFO architecture

Figure 363. Device-mode FIFO address mapping and AHB FIFO access mapping

IN endpoint Tx FIFO #n
IN endpoint Tx FIFO #1
IN endpoint Tx FIFO #0
DFIFO push access
Any OUT endpoint DFIFO pop
30.11.1

Peripheral Rx FIFO

The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT
endpoints. Received packets are stacked back-to-back until free space is available in the
Rx-FIFO. The status of the received packet (which contains the OUT endpoint destination
number, the byte count, the data PID and the validity of the received data) is also stored by
the core on top of the data payload. When no more space is available, host transactions are
NACKed and an interrupt is received on the addressed endpoint. The size of the receive
FIFO is configured in the receive FIFO Size register (GRXFSIZ).
1039/1422
DFIFO push access
from AHB
MAC pop
DFIFO push access
from AHB
MAC pop
from AHB
MAC pop
access from AHB
MAC push
Doc ID 018909 Rev 4
Dedicated Tx
FIFO #n control
(optional)
. .
.
Dedicated Tx
FIFO #1 control
(optional)
Dedicated Tx
FIFO #0 control
(optional)
Rx FIFO control
Single data
FIFO
DIEPTXF2[31:16]
Tx FIFO #n
packet
DIEPTXFx[15:0]
. .
.
DIEPTXF2[15:0]
Tx FIFO #1 packet
DIEPTXF1[31:16]
DIEPTXF1[15:0]
Tx FIFO #0 packet GNPTXFSIZ[31:16]
GNPTXFSIZ[15:0]
GRXFSIZ[31:16]
Rx packets
A1 = 0
RM0090
. .
.
(Rx start
address
fixed to 0)
ai15611