Hash Context Swap Registers (Hash_Csrx) - ST STM32F40 Series Reference Manual

Hash processor (HASH)
22.4.8

HASH context swap registers (HASH_CSRx)

Address offset: 0x0F8 to 0x1C0
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For HASH_CSR0 register: Reset value is 0x0000 0002.
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For others registers: Reset value is 0x0000 0000 , except for STM32F42xxx and
STM32F43xxx devices where the HASH_CSR2 register reset value is 0x2000 0000
Additional registers are available from 0x1C1 to 0x1CC on STM32F42xxx and
STM32F43xxx
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Reset value: 0x0000 0000.
These registers contain the complete internal register states of the hash processor, and are
useful when a context swap has to be done because a high-priority task has to use the hash
processor while it is already in use by another task.
When such an event occurs, the HASH_CSRx registers have to be read and the read values
have to be saved somewhere in the system memory space. Then the hash processor can
be used by the preemptive task, and when hash computation is finished, the saved context
can be read from memory and written back into these HASH_CSRx registers.
HASH_CSRx
Address offset: 0x0F8 to 0x1C0 on STM32F405xx/07xx and STM32F415xx/17xx
Address offset: 0x0F8 to 0x1CC on STM32F42xxx and STM32F43xxx
31 30 29
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15 14 13
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621/1422
28 27 26 25
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12 11 10 9
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Doc ID 018909 Rev 4
24 23 22 21
CSx
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8 7 6 5
CSx
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20 19 18 17
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4 3 2 1
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RM0090
16
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0
rw