Figure 281. Txe/Bsy In Slave Transmit-Only Mode (Bidimode=0 And Rxonly=0) In The Case Of - ST STM32F40 Series Reference Manual

RM0090

Figure 281. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of

continuous transfers
Example in slave mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
software writes software waits
0xF1 into until TXE=1 and
SPI_DR writes 0xF2 into
SPI_DR
Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)
In this mode, the procedure is similar to the procedure in Transmit-only mode except that the
BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling the
SPI.
Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)
In this mode, the procedure can be reduced as described below (see
1. Set the RXONLY bit in the SPI_CR2 register.
2. Enable the SPI by setting the SPE bit to 1:
a)
b)
3. Wait until RXNE=1 and read the SPI_DR register to get the received data (this clears
the RXNE bit). Repeat this operation for each data item to be received.
This procedure can also be implemented using dedicated interrupt subroutines launched at
each rising edge of the RXNE flag.
Note: If it is required to disable the SPI after the last transfer, follow the recommendation described
in Section 27.3.8: Disabling the SPI on page
DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by hardware
software waits
until TXE=1 and
writes 0xF3 into
SPI_DR
In master mode, this immediately activates the generation of the SCK clock, and
data are serially received until the SPI is disabled (SPE=0).
In slave mode, data are received when the SPI master device drives NSS low and
generates the SCK clock.
Doc ID 018909 Rev 4
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
software waits until TXE=1 software waits until BSY=0
815.
Serial peripheral interface (SPI)
DATA 3 = 0xF3
set by hardware
reset by hardware
Figure 282):
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