Configuring The Spi In Slave Mode; Figure 273. Data Clock Timing Diagram - ST STM32F40 Series Reference Manual

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1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.

Data frame format

Data can be shifted out either MSB-first or LSB-first depending on the value of the

LSBFIRST bit in the SPI_CR1 Register.

Each data frame is 8 or 16 bits long depending on the size of the data programmed using

the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for

transmission and/or reception.

Configuring the SPI in slave mode

In the slave configuration, the serial clock is received on the SCK pin from the master

device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data

transfer rate.

It is recommended to enable the SPI slave before the master sends the clock. If not,

undesired data transmission might occur. The data register of the slave needs to be ready

before the first edge of the communication clock or before the end of the ongoing

communication. It is mandatory to have the polarity of the communication clock set to the

steady state value before the slave and the master are enabled.

Follow the procedure below to configure the SPI in slave mode:

8 or 16 bits depending on the Data frame format bit (see DFF in SPI_CR1)

Capture strobe

8 or 16 bits depending on the Data frame format bit (see DFF in SPI_CR1)

Capture strobe

Doc ID 018909 Rev 4

Serial peripheral interface (SPI)

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