Data Alignment; Channel-Wise Programmable Sampling Time; Figure 38. Right Alignment Of 12-Bit Data; Figure 39. Left Alignment Of 12-Bit Data - ST STM32F40 Series Reference Manual

RM0090
11.4

Data alignment

The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in
The converted data value from the injected group of channels is decreased by the user-
defined offset written in the ADC_JOFRx registers so the result can be a negative value.
The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.

Figure 38. Right alignment of 12-bit data

Injected group
SEXT
Regular group
0

Figure 39. Left alignment of 12-bit data

Injected group
SEXT
Regular group
D11
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 40.

Figure 40. Left alignment of 6-bit data

Injected group
SEXT
Regular group
0
11.5

Channel-wise programmable sampling time

The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
SEXT SEXT SEXT D11 D10
0 0 0 D11 D10
D11 D10 D9 D8 D7
D10 D9 D8 D7
SEXT SEXT SEXT SEXT SEXT
0 0 0 0
Doc ID 018909 Rev 4
D9 D8 D7 D6
D9 D8 D7 D6
D6 D3
D5 D4
D6 D5 D4 D3 D2
SEXT SEXT SEXT
D5
0 0 0 D5 D4
Analog-to-digital converter (ADC)
Figure 38 and Figure
D5 D4 D3 D2
D5 D4 D3 D2
D2 D1 D0 0
D1 D0 0 0
D3 D2 D1
D4
D3 D2 D1 D0
39.
D1 D0
D1 D0
ai16050
0 0
0 0
ai16051
D0 0
0 0
ai16052
272/1422