ST STM32F40 Series Reference Manual page 757

Universal synchronous asynchronous receiver transmitter (USART)
Table 108. Error calculation for programmed baud rates at f
oversampling by 16
Baud rate7
S.No Desired
5 38.4 KBps 38.462 KBps
6 57.6 KBps 57.554 KBps
7 115.2 KBps 115.942 KBps
8 230.4 KBps 228.571 KBps
9 460.8 KBps 470.588 KBps
10 921.6 KBps
11 2 MBps
12 3 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 109. Error calculation for programmed baud rates at f
oversampling by 8
Baud rate
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps
5 38.4 KBps
6 57.6 KBps
7 115.2 KBps
8 230.4 KBps
9 460.8 KBps
10 921.6 KBps
757/1422
(1)
(continued)
Oversampling by 16 (OVER8=0)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
13
8.6875
4.3125
2.1875
1.0625
NA NA
NA NA
NA NA
(1)
Oversampling by 8 (OVER8 = 1)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 833.375
2.4 KBps 416.625
9.604 KBps 104.125
19.185 KBps 52.125
38.462 KBps 26
57.554 KBps 17.375
115.942 KBps 8.625
228.571 KBps 4.375
470.588 KBps 2.125
888.889 KBps 1.125
Doc ID 018909 Rev 4
= 8 MHz or f
PCLK
% Error =
(Calculated -
Actual
Desired) B.rate /
Desired B.rate
0.16 38.339 KBps
0.08 57.692 KBps
0.64 115.385 KBps
0.79 230.769 KBps
2.12 461.538 KBps
NA
NA
NA
= 8 MHz or f
PCLK
% Error =
(Calculated -
Desired)
Actual
B.rate /
Desired
B.rate
0 1.2 KBps
0.01 2.4 KBps
0.04 9.6 KBps
0.08 19.2 KBps
0.16 38.339 KBps
0.08 57.692 KBps
0.64 115.385 KBps
0.79 230.769 KBps
2.12 461.538 KBps
3.55 923.077 KBps
= 12 MHz,
PCLK
f = 12 MHz
PCLK
Value
programmed
in the baud
rate register
19.5625
13
6.5
3.25
1.625
NA NA
NA NA
NA NA
=12 MHz,
PCLK
f = 12 MHz
PCLK
Value
programmed
in the baud
rate register
1250
625
156.25
78.125
39.125
26
13
6.5
3.25
1.625
RM0090
% Error
0.16
0.16
0.16
0.16
0.16
NA
NA
NA
% Error
0
0
0
0
0.16
0.16
0.16
0.16
0.16
0.16