Rtc Wakeup Timer Register (Rtc_Wutr) - ST STM32F40 Series Reference Manual

Real-time clock (RTC)
Bits 31:24 Reserved
Bit 23 Reserved, must be kept at reset value.
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
Note: PREDIV_A [6:0]= 000000 is a prohibited value.
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
Note: This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to
page 630
This register is write protected. The write access procedure is described in
write protection on page
23.6.6

RTC wakeup timer register (RTC_WUTR)

Address offset: 0x14
Power-on reset value: 0x0000 FFFF
System reset: not affected
31 30 29
15 14 13
rw rw rw
Bits 31:16 Reserved
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
Note: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
Note: This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in
write protection on page
649/1422
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
630.
28 27 26 25
12 11 10 9
rw rw rw rw
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.
630.
Doc ID 018909 Rev 4
Calendar initialization and configuration on
24 23 22 21
Reserved
8 7 6 5
WUT[15:0]
rw rw rw rw
RTC register
20 19 18 17
4 3 2 1
rw rw rw rw
RTC register
RM0090
16
0
rw