Pwm Mode; Figure 182. Output Compare Mode, Toggle On Oc1 - ST STM32F40 Series Reference Manual

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PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined

by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx

output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. You must enable the corresponding preload register by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in

upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event

occurs, before starting the counter, you have to initialize all the registers by setting the UG

bit in the TIMx_EGR register.

The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.

It can be programmed as active high or active low. The OCx output is enabled by the CCxE

bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine

whether TIMx_CNT ≤ TIMx_CCRx.

The timer is able to generate PWM in edge-aligned mode only since the counter is

PWM edge-aligned mode

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is

high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in

TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at

'1'. If the compare value is 0 then OCxRef is held at '0'.

aligned PWM waveforms in an example where TIMx_ARR=8.

Write B201h in the CC1R register

Doc ID 018909 Rev 4

General-purpose timers (TIM9 to TIM14)

Match detected on CCR1

Interrupt generated if enabled

shows some edge-

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