Can Mailbox Registers - ST STM32F40 Series Reference Manual

RM0090
Bits 25:24 SJW[1:0]
These bits define the maximum number of time quanta the CAN hardware is allowed to
lengthen or shorten a bit to perform the resynchronization.
t
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 TS2[2:0]
These bits define the number of time quanta in Time Segment 2.
t
Bits 19:16 TS1[3:0]
These bits define the number of time quanta in Time Segment 1
t
For more information on bit timing, please refer to
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 BRP[9:0]
These bits define the length of a time quanta.
t
24.9.3

CAN mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to
Section 24.7.5: Message storage on page 678
Transmit and receive mailboxes have the same registers except:
●
The FMI field in the CAN_RDTxR register.
●
A receive mailbox is always write protected.
●
A transmit mailbox is write-enabled only while empty, corresponding TME bit in the
CAN_TSR register set.
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level
depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.
CAN_RI0R
CAN_RDT0R
CAN_RL0R
CAN_RH0R
FIFO0
:
Resynchronization jump width
= t x (SJW[1:0] + 1)
RJW CAN
:
Time segment 2
= t x (TS2[2:0] + 1)
BS2 CAN
:
Time segment 1
= t x (TS1[3:0] + 1)
BS1 CAN
:
Baud rate prescaler
= (BRP[9:0]+1) x t
q PCLK
CAN_RI1R
CAN_RDT1R
CAN_RL1R
CAN_RH1R
FIFO1
Doc ID 018909 Rev 4
Controller area network (bxCAN)
Section 24.7.7: Bit timing on page
for detailed register mapping.
CAN_TI0R CAN_TI1R
CAN_TDT0R CAN_TDT1R
CAN_TDL0R CAN_TDL1R
CAN_TDH0R
CAN_TDH1R
Three Tx Mailboxes
680.
CAN_TI2R
CAN_TDT2R
CAN_TDL2R
CAN_TDH2R
694/1422