ST STM32F40 Series Reference Manual page 1010

RM0090
The operation mode register establishes the Transmit and Receive operating modes and
commands. The ETH_DMAOMR register should be the last CSR to be written as part of
DMA initialization.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 DTCEFD: Dropping of TCP/IP checksum error frames disable
Bit 25 RSF: Receive store and forward
Bit 24 DFRF: Disable flushing of received frames
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 TSF: Transmit store and forward
Bit 20 FTF: Flush transmit FIFO
Bits 19:17 Reserved, must be kept at reset value.
Ethernet (ETH): media access control (MAC) with DMA controller
Reserved
rw rs
When this bit is set, the core does not drop frames that only have errors detected by the
receive checksum offload engine. Such frames do not have any errors (including FCS error)
in the Ethernet frame received by the MAC but have errors in the encapsulated payload only.
When this bit is cleared, all error frames are dropped if the FEF bit is reset.
When this bit is set, a frame is read from the Rx FIFO after the complete frame has been
written to it, ignoring RTC bits. When this bit is cleared, the Rx FIFO operates in Cut-through
mode, subject to the threshold specified by the RTC bits.
When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive
descriptors/buffers as it does normally when this bit is cleared. (See
suspended on page 960)
When this bit is set, transmission starts when a full frame resides in the Transmit FIFO.
When this bit is set, the TTC values specified by the ETH_DMAOMR register bits [16:14] are
ignored.
When this bit is cleared, the TTC values specified by the ETH_DMAOMR register bits [16:14]
are taken into account.
This bit should be changed only when transmission is stopped.
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all
data in the Tx FIFO are lost/flushed. This bit is cleared internally when the flushing operation
is complete. The Operation mode register should not be written to until this bit is cleared.
Doc ID 018909 Rev 4
Reserved
rw rw rw rw
9 8 7 6 5 4 3
rw rw rw rw rw rw
Receive process
2 1 0
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