Figure 191. Counter Timing Diagram, Internal Clock Divided By 1; Figure 192. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F40 Series Reference Manual

RM0090
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):
●
The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)
●
The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.

Figure 191. Counter timing diagram, internal clock divided by 1

Figure 192. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 018909 Rev 4
31 32 33 34 35 36 00 01 02 03 04 05 06 07
0034
0035 0036 0000 0001 0002 0003
Basic timers (TIM6&TIM7)
528/1422