Figure 95. External Trigger Input Block; Figure 96. Control Circuit In External Clock Mode 2 - ST STM32F40 Series Reference Manual

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Advanced-control timers (TIM1&TIM8)

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Figure 95. External trigger input block

For example, to configure the upcounter to count each 2 rising edges on ETR, use the

following procedure:

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal.

gives an overview of the external trigger input block.

/1, /2, /4, /8

Counter clock = CK_CNT = CK_PSC

Counter register

Doc ID 018909 Rev 4

external clock

external clock

internal clock

(internal clock)

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