Adc Common Status Register (Adc_Csr) - ST STM32F40 Series Reference Manual

Analog-to-digital converter (ADC)

11.13.15 ADC Common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing it to 0 in the corresponding ADC_SR register.
31 30 29 28
15 14 13 12
OVR2 STRT2
Reserved
r
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 OVR3: Overrun flag of ADC3
Bit 20 STRT3: Regular channel Start flag of ADC3
Bit 19 JSTRT3: Injected channel Start flag of ADC3
Bit 18 JEOC3: Injected channel end of conversion of ADC3
Bit 17 EOC3: End of conversion of ADC3
Bit 16 AWD3: Analog watchdog flag of ADC3
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 OVR2: Overrun flag of ADC2
Bit 12 STRT2: Regular channel Start flag of ADC2
Bit 11 JSTRT2: Injected channel Start flag of ADC2
Bit 10 JEOC2: Injected channel end of conversion of ADC2
Bit 9 EOC2: End of conversion of ADC2
Bit 8 AWD2: Analog watchdog flag of ADC2
303/1422
27 26 25
Reserved
11 10 9
JSTRT
JEOC2 EOC2
2
ADC2
r r r r
This bit is a copy of the OVR bit in the ADC3_SR register.
This bit is a copy of the STRT bit in the ADC3_SR register.
This bit is a copy of the JSTRT bit in the ADC3_SR register.
This bit is a copy of the JEOC bit in the ADC3_SR register.
This bit is a copy of the EOC bit in the ADC3_SR register.
This bit is a copy of the AWD bit in the ADC3_SR register.
This bit is a copy of the OVR bit in the ADC2_SR register.
This bit is a copy of the STRT bit in the ADC2_SR register.
This bit is a copy of the JSTRT bit in the ADC2_SR register.
This bit is a copy of the JEOC bit in the ADC2_SR register.
This bit is a copy of the EOC bit in the ADC2_SR register.
This bit is a copy of the AWD bit in the ADC2_SR register.
Doc ID 018909 Rev 4
24 23 22
OVR3
8 7 6
AWD2 OVR1
Reserved
r
21 20 19 18
STRT3 JSTRT3 JEOC 3 EOC3
ADC3
r r r r
5 4 3 2
STRT1 JSTRT1 JEOC 1 EOC1
ADC1
r r r r
RM0090
17 16
AWD3
r r
1 0
AWD1
r r