ST STM32F40 Series Reference Manual page 744

RM0090
Through these pins, serial data is transmitted and received in normal USART mode as
frames comprising:
●
An Idle Line prior to transmission or reception
●
A start bit
●
A data word (8 or 9 bits) least significant bit first
●
0.5,1, 1.5, 2 Stop bits indicating that the frame is complete
●
This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit
fraction
●
A status register (USART_SR)
●
Data Register (USART_DR)
●
A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.
●
A Guardtime Register (USART_GTPR) in case of Smartcard mode.
Refer to
The following pin is required to interface in synchronous mode:
● SCLK: Transmitter clock output. This pin outputs the transmitter data clock for
synchronous transmission corresponding to SPI master mode (no clock pulses on start
bit and stop bit, and a software option to send a clock pulse on the last data bit). In
parallel data can be received synchronously on RX. This can be used to control
peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity
are software programmable. In smartcard mode, SCLK can provide the clock to the
smartcard.
The following pins are required in Hardware flow control mode:
●
nCTS: Clear To Send blocks the data transmission at the end of the current transfer
when high
● nRTS: Request to send indicates that the USART is ready to receive a data (when
low).
Universal synchronous asynchronous receiver transmitter (USART)
Section 26.6: USART registers on page 782
Doc ID 018909 Rev 4
for the definitions of each bit.
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