Dma Transfer Completion - ST STM32F40 Series Reference Manual

RM0090
undesired value. The software may read the DMA_SxNDTR register to determine the
memory area that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST
bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB
memory port), single transactions will be generated to complete the FIFO flush.
Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and
the FIFO threshold level is not used. This mode is useful when the system requires an
immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-to-
peripheral mode, the DMA preloads one data from the memory to the internal FIFO to
ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with
a high priority.
This mode is restricted to transfers where:
●
The source and destination transfer widths are equal and both defined by the
PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don't care)
●
Burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR
are don't care)
Direct mode must not be used when implementing memory-to-memory transfers.
9.3.13

DMA transfer completion

Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR or
DMA_HISR status register:
●
In DMA flow controller mode:
–
–
●
In Peripheral flow controller mode:
–
–
Note: The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in noncircular mode, after the end of the transfer (that is when the
number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR
register is cleared by Hardware) and no DMA request is served unless the software
reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).
The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode
The stream is disabled before the end of transfer (by clearing the EN bit in the
DMA_SxCR register) and (when transfers are peripheral-to-memory or memory-
to-memory) all the remaining data have been flushed from the FIFO into the
memory
The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
The stream is disabled by software, and (when the DMA is operating in peripheral-
to-memory mode) the remaining data have been transferred from the FIFO into
the memory
Doc ID 018909 Rev 4
DMA controller (DMA)
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